Evaluation of 3C-SiC/Si residual stress and curvatures along different wafer direction R. Anzalone n , A. Alberti, F. La Via Institute of Microelectronics and Microsystems (IMM), VIII Strada, 5, 95121 Catania, Italy article info Article history: Received 22 October 2013 Accepted 17 December 2013 Available online 24 December 2013 Keywords: 3C-SiC Hetero-epitaxy Wafer curvature abstract During the heteroepitaxial growth of a thin film on a thick substrate, important stresses arise in the grown material and may influence the physical properties of the film. The residual stresses result in a bending of the substrate/film system. In this work the evaluation of the wafer curvature and the residual stress along different crystallographic directions of the wafer was proposed. Performed by an interfero- metric optical profilometer, optical microscope and X-ray diffraction analysis, the curvature of the wafer along the [110] and [1 10] wafer directions was observed for hetero-epitaxial Cubic Silicon Carbide (3C-SiC) on Si (001) films. As a consequence of the stress generated during hetero-epitaxy, due to the difference in thermal expansion coefficient and lattice mismatch between the two materials, an asymmetric wafer curvature was observed. & 2014 Elsevier B.V. All rights reserved. 1. Introduction Silicon carbide (SiC) is considered to be one of the alternative semiconductor materials to Si for power electronics applications due to its excellent properties such as wide band gap, high breakdown field, and high thermal conductivity. The main reason that prevents the large-scale development of viable Cubic Silicon Carbide on Silicon substrate [3C-SiC/Si] tech- nology is the lattice mismatch (  20%) and the difference in thermal expansion coefficients (  23% at deposition temperature) between the (thin) cubic silicon carbide film (3C-SiC) and the (thick) silicon substrate, that are blamed for the generation of misfit dislocations and stacking faults (SF) at the interface. For these reasons, during the heteroepitaxial growth of a thin film on a substrate, important stresses arise in the grown material. The residual stress alters the lattice spacing and consequently changes the physical properties of the film. Therefore, stress relaxation has important implications with regard to the processing and quality of the epitaxy. Residual stress changes the mechanical response and/or the resonant fre- quency of the thin-film structure and may degrade the performance in MEMS devices. For example, the stress may change the mechan- ical response of the sensor, modifying the resonant frequency [1] of the microstructures, even causing sensor failure. Therefore, a better understanding of the stress relaxation mechanism could improve the exploitation of 3C-SiC devices and sensor technologies. In a thin-film/wafer system the residual stresses result in a bending of the wafer (wafer bow) [2]. Since the pioneering works of Nishino et al., [3], different studies of the film/substrate deformation induced by various growth processes [4,5], by different substrate orientation [6], by micro-machined substrate [7], or by wafer cut effect [8] have been proposed in literature in order to understand the stress/curvature behavior and/or minimize the wafer curvature in the 3C-SiC films. In this study, through different analysis performed on many samples, growth with different conditions and on different substrate dimensions, a non-symmetric curvature was observed in 3C-SiC on Si films as a function of wafer orientation. In order to evaluate the wafer curvature along different wafer directions ([110] and [1  10], parallel and orthogonal to the wafer flat directions), profilometer scan, optical and XRD analysis have been performed. 2. Experiment In this experiment, 3C-SiC heteroepitaxial multi-step growth processes were used to reduce the defect density in the growing layer and to improve its crystalline quality. The epitaxial films were grown in a hot-wall Chemical Vapor Deposition reactor on 4, 6 and 8 in. (100) Si-oriented substrates with thickness of t Si ¼ 275 μm, t Si ¼ 1500 μm and t Si ¼ 850 μm, respectively. For the 4 and 8 in.-wafer the CVD growth process in the low pressure regime was carried out using trichlorosilane (SiHCl 3 ), ethylene (C 2 H 4 ) and hydrogen (H 2 ) as the silicon and carbon supply and gas carrier, respectively. While, for the 4 in.-wafer the process was carried out using Silane (SiH 4 ) instead of trichlorosilane as the silicon supply. For all the samples the multi-step growth processes were performed beginning with the buffer layer formation at 1120 1C (20 nm of 3C-SiC with no Si supply) followed by the Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/matlet Materials Letters 0167-577X/$ - see front matter & 2014 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.matlet.2013.12.067 n Corresponding author. E-mail address: ruggero.anzalone@imm.cnr.it (R. Anzalone). Materials Letters 118 (2014) 130–133