On Testability of Multiple Precharged Domino Logic Th. Haniotakis’, Y. Tsiatouhas’, D. Nikolos2 and C. Efstathiou3 ‘LSD S. A 2Dept. of Computer Engineering and Informatics 22, K. Varnali Str. 1.52 33 Halandri, Greece University of Patras, 26 500, Rio, Patras, Greece e-mail: {haniotakis, tsiatouhas@isd.gr) e-mail : nikolosd@ cti.gr 3Dept. of Informatics TEI of Athens, 122 IO, Egaleo, Athens, Greece e-mail.. cefsta@teiath.gr Abstract Domino circuits are increasingly popular because they offer a significant performance boost over static ones. An inherent problem with domino CMOS gates is that under spectjic input conditions the charge redistribution between parasitic capacitances at internal nodes of the circuit can destroy the noise margin and cause glitches at the output of a domino gate. Among the dominant solutions proposed, in the open literature, to overcome this problem is the technique of internal nodes multiple precharging. However the added precharge transistors are not testable for stuck-open and stuck-on faults. Undetectable stuck-open faults on these transistors cause reduction of the noise margins of the gate. Then the operation of the circuit in the Jield is sensitive to environmental factors, such as noise. In this paper we propose a new internal nodes multiple precharging scheme that leads to testable designs for stuck-open and stuck-on faults. 1. Introduction Domino CMOS logic gives circuits with area comparable to static NMOS or pseudo-NMOS, that is, much smaller than static CMOS and runs 1.5 - 2 times faster than full static CMOS logic [l, 21. Due to these features domino circuits are widely used in high - performance CMOS microprocessors 121. In Domino logic a single clock is used to precharge and evaluate a cascaded set of dynamic logic blocks [3]. This circuitry incorporates a static CMOS inverter into each logic gate as shown in Figure 1. During the precharge phase (WO) all output nodes (F’) of the dynamic gates are precharged to high, through the transistor MP, and thus the outputs (F) of the corresponding inverters are precharged to low. Since all transistors of subsequent dynamic gates are fed from such inverters, these will be turned off during the precharge phase. Next, during the evaluation phase: nodes F’ are either discharged through transistor MN or they remain high, according to the realized function. Thus the outputs F of the inverters either go to high or remain low, respectively. It should be noted that in Domino logic the transition of nodes F is always from low to high and it is rippled through the logic from the primary inputs to the primary outputs. Since there are cascaded logic blocks, the evaluation of a stage causes the next stage to evaluate and so on. T VDD F MN I I vss Figure 1: A Domino logic circuit