INVITED PAPER Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective When the supply voltage is less than the threshold value needed to sustain normal operation, useful digital circuit performance can be obtained by using leakage current for computation. By Sumeet Kumar Gupta , Arijit Raychowdhury, and Kaushik Roy, Fellow IEEE ABSTRACT | Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to pa- rameter variations. However, operating digital logic and mem- ory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimi- zations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipa- tion point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leak- age current can be useful for other applications like thermal sensors. KEYWORDS | Adaptive beta ratio modulation; double gate MOSFETs; low-voltage design; parallelization and pipelining; parameter variations; SRAM; steep devices; subthreshold logic I. INTRODUCTION Increasing demand for battery-operated mobile platforms like laptops, cellular phones, etc., has led to the require- ment for circuit designs to be more power aware. Since energy has a square dependence on the power supply volt- age ðV dd Þ, power dissipation of a circuit can be significantly reduced by operating at a lower supply voltage [1]–[3]. Voltage scaling also assumes significance for highly scaled devices, in order to keep the electric field well below its critical value. Scaling of device dimensions compensates for the loss of performance due to supply voltage reduction; however, secondary effects like gate leakage, reverse bias source-substrate and drain-substrate band-to-band tunnel- ing (BTBT) currents [4]–[6], drain induced barrier lowering (DIBL) and other short channel effects increase significantly, thus adversely affecting the functionality of the device. Hence, for systems which require high perfor- mance, coping with the secondary effects becomes im- portant and generally involves a trade-off between power, performance, area or cost. For instance, halo implants [7] are used to tackle the problem of short channel effects; however, this leads to an increase in the process complexity and larger junction capacitance. Threshold voltage may be Manuscript received November 11, 2008; revised August 30, 2009 and October 2, 2009. Current version published January 20, 2010. This work was supported in part by SRC, DARPA and Boeing. S. K. Gupta and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: guptask@purdue.edu; kaushik@ecn.purdue.edu). A. Raychowdhury is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: arijit.raychowdhury@intel.com). Digital Object Identifier: 10.1109/JPROC.2009.2035060 160 Proceedings of the IEEE | Vol. 98, No. 2, February 2010 0018-9219/$26.00 Ó2010 IEEE