INTEGRATION, the VLSI journal 41 (2008) 161–170 A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver L. Bissi, P. Placidi à , G. Baruffa, A. Scorzoni Dipartimento di Ingegneria Elettronica e dell’Informazione (DIEI), Universita` degli Studi di Perugia, via G. Duranti 93, I-06125 Perugia, Italy Received 14 November 2005; received in revised form 2 April 2007; accepted 2 April 2007 Abstract This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse. r 2007 Elsevier B.V. All rights reserved. Keywords: Viterbi decoder; Software defined radio; Field Programmable Gate Array (FPGA); Configurable and programmable architecture 1. Introduction In digital communication systems, convolutional enco- ding coupled with Viterbi algorithm (VA) decoding is widely used for its capability to protect information data from the impairments (e.g. noise, multipath, fading) introduced by the transmission medium. When a poten- tially corrupted sequence of symbols is received, the VA [1] determines the most likely transmitted sequence by exploiting a maximum likelihood criterion. The idea behind the Viterbi decoder (VD) is quite simple, in spite of its inherent implementation difficulty. Moreover, there is a wide gap in complexity with the transmission side, where convolutional encoding can easily be imple- mented. Since convolutional codes are represented by a state trellis, the decoder is a finite state machine that explores the transitions between states, stores them in a large memory, and comes to a final decision on a sequence of transitions after some latency due to the constraint length of the input code [1]. Decisions are usually taken by considering the transition metrics among states, which are updated in terms of either Euclidean or Hamming distance with the error-corrupted received sequence. The performance of convolutional codes strongly depends on their minimum distance, which in turn depends on the constraint length and coding rate. As a consequence, in order to increase the gain with respect to the uncoded case, there is a continuous trend towards increasing such parameters. Thus, complexity may grow up to a limit where classic implementation techniques are no longer viable. Recently, adaptive Viterbi decoding (AVD) for the algorithmic part [2,3] and systolic architectures for the implementation aspects [4,5] are increasing their popularity in the technical literature. In the AVD approach, only a subset of the states is stored and processed, significantly reducing computation and storage resources at the expense of a small performance loss. At the same time, a highly complex VD someway loses its advantages, when it is adopted to decode sequences transmitted on a low-noise channel. In this case, low minimum distance codes are more suitable for achieving a good performance, and a higher bit rate can be transmitted by lowering the coding rate. Therefore, programmability ARTICLE IN PRESS www.elsevier.com/locate/vlsi 0167-9260/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2007.04.001 à Corresponding author. Tel.: +39 075 5853636; fax: +39 075 5853654. E-mail address: pisana.placidi@diei.unipg.it (P. Placidi).