2236 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 10, OCTOBER 2005 Analysis of Temperature-Induced Saturation Threshold Voltage Degradation in Deep-Submicrometer Ultrathin SOI MOSFETs Marcelo Antonio Pavanello, Member, IEEE, João Antonio Martino, Eddy Simoen, and Cor Claeys, Senior Member, IEEE Abstract—This paper presents a systematic study of the tem- perature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demon- strated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body in- creases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation. Index Terms—Drain-induced barrier lowering (DIBL), fully de- pleted, low temperature, MOSFET, silicon-on-insulator (SOI). I. INTRODUCTION T HE ADVANTAGES of fully depleted silicon-on-insu- lator (SOI) transistors over bulk counterpart have been extensively reported in the past few years, such as steeper sub- threshold slope, allowing threshold voltage reduction without increasing the off-state current. However, as the device body region is kept floating, the action of the parasitic bipolar struc- ture associated to the MOSFET is a major concern in SOI. As the device dimension is reduced, the susceptibility of the transistor to short-channel effects (SCE) is monitored in several ways such as threshold voltage roll-off or variation with the drain bias rise, the drain-induced barrier lowering (DIBL). The DIBL increases exponentially when the effective channel length decreases and becomes crucial in deep-submi- crometer technologies [1]. The rolloff is generally solved by adopting lateral channel engineering as the halo or pocket implantation [2], [3]. On the other hand, the combination of Manuscript received December 10, 2004; revised June 9, 2005. The review of this paper was arranged by Editor R. Shrivastava. M. A. Pavanello and J. A. Martino are with the Departamento de Engen- haria Elétrica, Centro Universitário da FEI, São Bernardo do Campo 09850-901, Brazil. and also with the Laboratório de Sistemas Integráveis, Universidade de Sao Paulo, Sao Paulo 05508-900, Brazil (e-mail: pavanello@fei.edu.br). E. Simoen is with the IMEC, Leuven B-3001, Belgium. C. Claeys is with the IMEC, Leuven B-3001, Belgium, and also with the Department of Electrical Engineering, KU Leuven, Leuven, Belgium. Digital Object Identifier 10.1109/TED.2005.856799 floating-body operation and the increment of lateral electric field when shrinking the dimensions hardly affect the physics associated to DIBL in SOI transistors, differently to bulk tran- sistors where the DIBL is only due to the barrier lowering at the source [4]. Reported works indicate that the threshold voltage of SOI transistors can suffer a significant variation when the drain bias is increased due to the activation of this parasitic bipolar structure, resulting in higher DIBL than in bulk [5], [6]. The reduction in saturation increases the off-state current affecting the performance and static power dissipation of SOI circuits. An option for improving the device characteristics without scaling the dimensions is the reduction of the environment tem- perature, which increases the carrier mobility and velocity satu- ration, reduces the subthreshold slope and allows for high drive current [7]. In addition, by cooling the device, the DIBL occur- rence in bulk MOSFETs has been reported to be nearly temper- ature insensitive [8] or, at least, not worst than at room temper- ature [9], [10]. On the other hand, the use of halo implantation has been demonstrated to degrade the DIBL of floating-body partially depleted SOI nMOSFETs in cryogenic operation [11]. The goal of this work is to demonstrate that the temperature reduction of halo implanted fully depleted SOI devices can drastically emphasize the threshold voltage variation with drain bias, or simply DIBL, of nMOSFETs. The DIBL of SOI pMOSFETs remains temperature insensitive in the studied range. This investigation is made using both experimental and two-dimensional simulations. Finally, an investigation of some scaling parameters on SOI such as buried oxide thickness and halo implantation is performed. Section II presents the set of measurements performed in both nMOS and pMOS deep-submicrometer SOI MOSFETs, indicating the tempera- ture-dependent DIBL. In Section III a physical insight on the enhanced DIBL with temperature lowering is presented based on two-dimensional simulations and model. The conclusions of this paper are pointed out in Section IV. II. EXPERIMENTAL RESULTS The measurements were performed in both nMOS and pMOS FD SOI transistors with a mask channel length (L) of 0.13 m and a channel width (W) of 10 m. Standard ELTRAN wafers with 100-nm buried oxide thickness where employed. The active regions are isolated by using a Shallow Trench Isola- tion technique. The gate stack consists of a 2.5 nm thick nitrided 0018-9383/$20.00 © 2005 IEEE