Study of Thermal Stability of HfO x N y /Ge Capacitors Using Postdeposition Annealing and NH 3 Plasma Pretreatment Chao-Ching Cheng, a Chao-Hsin Chien, a,b,z Guang-Li Luo, b Chun-Hui Yang, b Mei-Ling Kuo, b Je-Hung Lin, a Chih-Kuo Tseng, a and Chun-Yen Chang a a Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300 b National Nano Device Laboratory, Hsinchu, Taiwan 300 We studied the thermal stability of the as-deposited HfO x N y thin ﬁlms on the Ge substrate by employing rapid thermal annealing. After undergoing high-temperature processing, we observed several interesting physical and electrical features presented in the HfO x N y /Ge system, including a large Ge out-diffusion 15 atom % into high-k ﬁlms, positive shift of the ﬂatband voltage, severe charge trapping, and increased leakage current. These phenomena are closely related to the existence of GeO x defective layer and the degree of resultant GeO volatilization. We abated these undesirable effects, especially for reducing the amount of Ge incorporation 5 atom % and the substoichiometric oxide at dielectric-substrate interface, through performing NH 3 plasma pretreatment on the Ge surface. These improvements can be interpreted in terms of a surface nitridation process that enhanced the thermal stability of the high-k /Ge interface. In addition, we measured that the conductance loss in inversion was still high and it revealed independence with respect to gate bias, reﬂecting the fact that the minority carriers in Ge can rapidly respond either through a diffusion mechanism or through midgap trap states residing in Ge bulk substrates. © 2007 The Electrochemical Society. DOI: 10.1149/1.2734875 All rights reserved. Manuscript submitted December 4, 2006; revised manuscript received February 27, 2007. Available electronically May 10, 2007. Recently, Ge-channel devices, including bulk Ge, 1,2 strained Ge, 3 and Ge-on-insulator GOI 4 systems, integrated with high-k gate di- electrics have attracted considerable research interest. Although transistors were originally fabricated on Ge substrates, the lack of a stable Ge native oxide has been an obstacle in complementary- metal-oxide-semiconductor CMOS device realization with Ge. Therefore, silicon has been used in CMOS technology for many decades because of the better qualities of its native oxide, such as a low leakage current, low interface state density, and good thermal stability. With the further scaling of device and gate oxide dimen- sions down to the nanometer range, however, the leakage current density in SiO 2 has become much higher than 2 mA/cm 2 , which is the maximum concession for low-power applications. 5 Conse- quently, higher dielectric constant materials with a thicker physical thickness are being introduced to suppress the concern of excessive gate leakage while maintaining the equivalent oxide thickness EOT of the scaled devices. Presently, hafnium-based oxides or oxynitrides, e.g., HfO 2 , HfON, and HfSiON, are the uppermost candidates for application among all of the potential high-k dielectrics. Both Si and SiGe metal oxide semiconductor ﬁeld-effect transistors MOSFETs integrated with Hf-based gate dielectrics exhibit admirable properties, 6-8 but they also reveal undesirable surface carrier mobility degradation behavior. 9,10 Changing the substrate from silicon to germanium might be a possible solution to this problem because Ge has a higher carrier mobility relative to that of Si. From recent advances in the deposition of high-k materials, Ge MOSFETs incorporating high-k gate dielectrics have exhibited some promising performance. 11,12 In this study, we ﬁrst investigated the physical and electrical character- istics of HfO x N y thin ﬁlms deposited on bulk Ge substrates and then determined the impact of thermal annealing processing on the entire capacitor structure. Recent reports have described that annealing a cleaned Ge substrate in a NH 3 13 or SiH 4 14 gas ambient, prior to deposition of a high-k dielectric, further improves the MOS proper- ties on Ge. In this paper we describe our investigation of the effects on the passivation efﬁciency when using NH 3 plasma on a Ge sub- strate. We found that the overall MOS structures had higher thermal stability and showed improved electrical characteristics. In addition, we provide a scheme outlining the charge trapping mechanism. Experimental Metal–insulator–semiconductor MIS capacitors were fabricated on n-type Ge substrates resistivity 8–12  cm, which were pre- cleaned through a cyclic rinse involving a diluted HF dip and deion- ized water. After wet cleaning, the NH 3 plasma exposure on the Ge surface of some samples was performed in the plasma-enhanced chemical vapor deposition PECVD. HfO x N y thin ﬁlms were sub- sequently deposited through reactive sputtering in a Ar + N 2 ambi- ent with a pure Hf target, followed by annealing in a N 2 atmosphere containing residual oxygen; various postdeposition annealing tem- peratures 500 and 600°C and durations 30 s and 5 min were employed. Next, a platinum Pt dot was deposited using electron beam evaporation through a shadow mask. For evaluating the ther- mal stability of the Pt/high-k /Ge structures, the annealing conditions described above were performed after metallization. The detailed deposited conditions and fabrication procedures have been described previously. 15 Transmission electron microscopy TEM and secondary-ion mass spectroscopy SIMS were employed to inves- tigate the entire structure and Ge incorporation behavior, respec- tively. In addition, we carried out ex situ XPS measurements using an Al K source  1486.6 eV to examine the effects of surface plasma nitridation on the dielectric-substrate interface and evaluate the Ge contamination level within the top high-k ﬁlms. In electrical characterization, the capacitance-voltage C-V and conductance- voltage G-V curves were measured using an HP4284 LCR meter, while the current-voltage I-V characteristics were measured using a Keithley 4200 semiconductor analyzer system. We further ex- tracted the series resistance and external inductance or capacitance in measurements and then applied as a correction to the measured capacitance and conductance. 16,17 The value of the effective trapped charge density  N eff  was determined quantitatively by measuring the hysteresis width at ﬂatband voltage  V FB  in the bidirectional C-V sweeps. 18 The interface state density  D it  was estimated from both high-low frequency capacitance method 19 and the G-V char- acteristics using Hill’s method. 20 Results and Discussion TEM image and SIMS depth proﬁles.— Figure 1 shows cross- sectional TEM image of as-deposited Pt/HfO x N y /Ge structure. We characterized that the thicknesses of the HfO x N y bulk ﬁlm and the interfacial layer IL were ca. 73 and 19 Å, respectively. When HfO x N y /Ge system undergoes high-temperature process, of primary interest is the resultant germanium diffusion in the overlying HfO x N y ﬁlms. As the SIMS depth proﬁles illustrated in Fig. 2, we observed a large Hf tail, a known SIMS artifact, at the end of the HfO x N y layer, and ion yield enhancements of both Ge and Hf at the beginning of the Ge substrate. Discarding these artiﬁcial phenom- ena, a U-shaped distribution of Ge did exist inside the overlying z E-mail: chchien@faculty.nctu.edu.tw Journal of The Electrochemical Society, 154 7 G155-G159 2007 0013-4651/2007/1547/G155/5/$20.00 © The Electrochemical Society G155 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 140.113.38.11 Downloaded on 2014-04-26 to IP