858 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 3, MARCH 2008 Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs Min Zhang, Joachim Knoch, Shi-Li Zhang, Sebastian Feste, Michael Schr ¨ oter, Member, IEEE, and Siegfried Mantl, Member, IEEE Abstract—The inhomogeneity of Schottky-barrier (SB) height Φ B is found to strongly affect the threshold voltage V th of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate ox- ide thickness t ox and SOI body thickness t si ; the contribution of inhomogeneity to the V th variation becomes less pronounced with smaller t ox and/or larger t si . Moreover, an enhanced V th variation is observed for devices with dopant segregation used for reduction of the effective Φ B . Furthermore, a multigate structure is found to help suppress the V th variation by improving carrier injection through reduction of its sensitivity to the Φ B inhomogeneity. A new method for extraction of Φ B from room temperature transfer characteristics is also presented. Index Terms—Ambioplar, Schottky barrier inhomogene- ity, Schottky barrier MOSFET, silicon-on-insulator, threshold voltage. I. INTRODUCTION A S THE CONTINUED down-scaling becomes increas- ingly challenging, solutions are urgently needed to meet the requirements of the International Technology Roadmap for Semiconductors (ITRS) [1]. Schottky-barrier (SB)-MOSFETs present a promising alternative to conventional MOSFETs, because the metallic source–drain contacts offer abrupt junction and low extrinsic parasitics [2], [3]. However, the performance of SB-MOSFET still falls behind that of con- ventional MOSFET. Therefore, intensive research has been devoted to improving the performance of SB-MOSFETs. Recently, a number of approaches that lead to significant improvements of SB-MOSFETs have been demonstrated. They include the use of silicides with lower Φ B (Φ Bn and Φ Bp ) Manuscript received July 6, 2007; revised October 16, 2007. The review of this paper was arranged by Editor C.-Y. Lu. M. Zhang was with the Institute of Bio- and Nanosystem-IBN1, Forschungszentrum J¨ ulich, D-52454 J¨ ulich, Germany. He is now with the Cypress Semiconductor Technology Corporation, Ltd., 201203 Shanghai, China. J. Knoch is with the IBM Research GmbH, Zurich Research Laboratory, 8803 R¨ uschilkon, Switzerland. S.-L. Zhang is with the State Key Laboratory of Application Specific In- tegrated Circuit (ASIC) and System, School of Microelectronics, Fudan Uni- versity, 200433 Shanghai, China, and also with the School of Information and Communication Technology, Royal Institute of Technology (KTH), SE-164 40 Stockholm, Sweden (e-mail: shilizhang@fudan.edu.cn). S. Feste is with the Institute of Bio- and Nanosystem-IBN1, Forschungszen- trum J¨ ulich, D-52454 J ¨ ulich, Germany. M. Schr¨ oter is with Dresden University of Technology, 01062 Dresden, Germany, and also with the University of California, San Diego, CA 92093 USA. S. Mantl is with the Institute of Bio- and Nanosystem-IBN1, Forschungszen- trum J¨ ulich, D-52454 J ¨ ulich, Germany, and also with the Aachen University of Technology (RWTH), 52062 Aachen, Germany. Digital Object Identifier 10.1109/TED.2007.915054 [4], [5], thin t ox , thin t si [6], or dopant segregation at the silicide– silicon interface [7], [8]. Since a tunneling barrier is involved that gives rise to an exponential dependence on Φ Bn (or Φ Bp ) of the injection of carriers (into the channel), the performance variation from device to device is a major concern for SB-MOSFETs. In particular, as SB-MOSFETs with dopant segregation are of par- ticular interest for next generations of CMOS technology [10], investigation of the reproducibility of such devices is becoming urgent. In this paper, the V th variation in devices with different geometric parameters as well as devices with dopant segregation will be investigated. An analysis of the distribution of V th shows that the V th variation induced by the Φ B inhomogeneity can be effectively suppressed by the use of thin t ox . The use of thin t si , on the other hand, leads to a larger spread in V th despite perfor- mance improvement. For devices with dopant segregation, the V th variation becomes slightly larger compared to the devices without dopant segregation. The statistical mean value of V th is used to extract the mean Φ B based on an analytical model. This approach is different from traditionally used current vs. voltage and temperature (I –V –T ) [9], [11], or capacitance–voltage (C–V ) [12] methods. The extracted mean Φ Bn for electron injection is 0.63 eV for devices with t ox = 3.5 nm and t si = ∼9 nm, 0.68 eV for devices with t ox = 3.5 nm and t si = ∼50 nm. Both Φ Bn values satisfactorily agree with the well-documented value determined by means of Schottky diodes [13]. Finally, it is experimentally demonstrated that a 15% reduction of the V th variation can be achieved by applying a back gate bias. II. SOI SB-MOSFET F ABRICATION SB-MOSFETs with fully nickel silicided source/drain elec- trodes were fabricated on <100> p-type doped SOI wafer (N A = 1 × 10 15 cm −3 ) with an initial silicon thickness of ∼100 nm. Three series of devices were prepared: 1) t si = ∼50 nm, but various t ox ; 2) t ox = 3.5 nm, but various t si ; and 3) t ox = 3.5 nm, t si = ∼50 nm with dopant segregation. Devices with different t si were realized by a cycle of dry/wet oxidation and modified standard cleaning (1:8:64 = NH 4 OH:H 2 O 2 :H 2 O at 65 ◦ C for 10 min). Devices with different gate oxide thick- nesses of 3.5 and 24 nm were realized by wet oxidation [14]. Immediately after the gate oxide formation, a 200 nm in situ n-doped poly-Si (N D > 1 × 10 20 cm −3 ) and 50-nm-thick SiO 2 were deposited by means of low-pressure chemical vapor de- position (LPCVD). The LPCVD layers were subsequently pat- terned by reactive ion etching. Ion implantation with different doses was only carried out for the devices with dopant segre- gation. After sidewall spacer formation and a diluted HF dip, 0018-9383/$25.00 © 2008 IEEE