Microelectronics Journal, 24 (1993) 647-657 Measurement and modeling of drain current DLTS in enhancement SOl MOSFETs xl R) O. -0 "0 H. Haddara Electronics and Communication Engineering Department, Ain Shams University, 1 El-Sarayat Street, Abbasia I1517, Cairo, Egypt M. T. Elewa Electrical Engineering Department, Zagazig University, Shobra, Cairo, Egypt S. Cristoloveanu LPCS, ENSERG, BP 257, F-38016 Grenoblecedex, France A new approach for current deep-level transient spectro- scopy (DLTS) in enhancement-mode MOSFETs is presented. The novelty of this approach is three-fold: (1) it improves the modeling of the transient drain current by directly calculating the transient variation of the inversion charge instead of that of the threshold voltage; (2) it accounts for the mobility field dependence and series resistance effects through a new current dependent mobi- lity law; and (3) it applies a combination of two already existing DLTS measurement procedures in order to avoid any temperature scanning. Measurements were carried out on n-channel enhance- ment mode MOSFETs fabricated on bulk Si as well as on SIMOX substrates. Deep-level traps were identified in SIMOX devices and the trap parameters (density, time- constant and trap level) were determined using the proposed method. 1. Introduction T he interface and bulk trap properties in MOS devices are currently investigated using various transient capacitance methods, namely the Zerbst technique and its alternatives [1] and the capacitance DLTS [2]. Transient drain current measurement in MOS transistors has recently been used for the same purpose. Techniques such as channel conductance DLTS [3] and drain current DLTS [4] were recently proposed to charactcrizc bulk traps in SOI material. In fact, the extraction of interface and/ or bulk trap properties from transient drain 0026-2692/93/$6.00 © 1993, Elsevier Science Publishers Ltd. 647