30 AT LAS I is a general-purpose, sin- gle-chip, gigabit, asynchronous-transfer-mode (AT M) switch with advanced architectural features. 1 A team from FO RT H and the Uni- versity of Crete designed AT LAS I for high- throughput and low-latency systems including wide-, local-, and system-area networks (WANs, LANs, and SANs). T he switch sup- ports a mixture of services in applications ranging from telecommunications to multi- media and multiprocessor NOWs (networks of workstations). AT LAS I’s architecture and basic internal organization appear elsewhere. 1 In this arti- cle, we present the design complexity and implementation cost of the chip and its vari- ous functions, and we evaluate the switch in view of these metrics. We estimate design complexity in terms of Verilog code size and approximate human effort. We measure implementation cost in terms of gates, flip-flops, SRAM bit counts, silicon area, and power consumption. We break these measurements down by function, rather than by hardware block. T hen, we eval- uate the design style and library used: semi- custom versus full-custom logic, and compiled memory availability. Finally, we evaluate the architecture of the switch in view of the design metrics. For high- cost functions, we discuss whether a different organization could decrease the cost, or whether the functions should be dropped entirely. In particular, we discuss backpressure, and demonstrate that its important benefits justify its cost. (For complete details, please see the paper we presented at the Hot Inter- connects 6 Symposium. 2 ) Overview of ATLAS I AT LAS I is a single-chip AT M switch with optional credit-based flow control. Its key fea- tures are • six million transistors in a 0.35-micron CMOS process; • 16 input ports (links), 16 output ports; • 622 Mbps per port, yielding 10-Gbps aggregate outgoing throughput; • gigabaud serial I/O links (IEEE 1355 HIC/HS—Heterogeneous InterConnect/ High Speed); • submicrosecond cut-through latency; • 256-cell shared buffer containing multi- ple logical output queues; • three levels of priorities, multicasting, header translation; • optional credit-based flow control (back- Georgios Kornaros, Dionisios Pnevmatikatos, Panagiota Vatsolaki, Georgios Kalokerinos, Chara Xanthaki, Dimitrios Mavroidis, Dimitrios Serpanos, and Manolis Katevenis FORTH and the University of Crete 0272-1732/99/$10.00  1999 IEEE ATLAS I: IM PLEM ENTING A S INGLE -C HIP ATM S W ITCH W ITH B ACKPRESSURE TO EVALUATE THE ARCHITECTURE OF ATLAS I, W E ANALYZED THE DESIGN COM PLEXITY AND SILICON COST OF THE CHIP ’ S INDIVIDUAL FUNCTIONS. OUR ANALYSIS SUGGESTS POSSIBLE IM PROVEM ENTS; CREDIT SUPPORT , HOW EVER , IS W ELL W ORTH ITS COST . .