POTRA: A Framework for Building Power Models for Next Generation Multicore Architectures [Tutorial Overview] Ramon Bertran Barcelona Supercomputing Center C. Jordi Girona 1-3 08034 Barcelona, Spain ramon.bertran@bsc.es Marc Gonzàlez Universitat Politècnica de Catalunya C. Jordi Girona 1-3 08034 Barcelona, Spain marc@ac.upc.edu Xavier Martorell Barcelona Supercomputing Center C. Jordi Girona 1-3 08034 Barcelona, Spain xavier.martorell@bsc.es Nacho Navarro Barcelona Supercomputing Center C. Jordi Girona 1-3 08034 Barcelona, Spain nacho.navarro@bsc.es Eduard Ayguadé Barcelona Supercomputing Center C. Jordi Girona 1-3 08034 Barcelona, Spain eduard.ayguade@bsc.es Categories and Subject Descriptors C.4 [Performance of Systems]: Modeling Techniques; C.4 [Performance of Systems]: Measurement Techniques General Terms Measurement, Experimentation Keywords Power estimation, Performance counters, DVFS 1. INTRODUCTION Controlling the trade-off between performance and power is a complex task that currently is addressed at different lev- els by hardware, firmware and system software. The effec- tiveness of a power management policy depends on many pa- rameters that require an actual understanding of the power and performance levels observed for a workload to effectively turn the appropriate knobs. One key aspect of any power management solution is that of relying on meaningful data that bring this understanding and explain the power, tem- perature and performance levels being generated within the architecture. Last generation multi-core chips have exposed the limita- tions for sensor distribution within the chip and the unfea- sibility of having per-core measurements. Besides, heuris- tics exclusively based on sensor distribution do not allow for predicting the effect on performance of any decision at the power management level. Alternative methods are required to get power, temperature and performance estimates: for instance, the IBM POWER7 includes power models based on hardware counters collected on a per-core basis that are used by the embedded firmware to perform the power man- agement. Copyright is held by the author/owner(s). SIGMETRICS’12, June 11–15, 2012, London, England, UK. ACM 978-1-4503-1097-0/12/06. Figure 1: Power model examples. Both models show similar accuracy, but Model 2 is more responsive than Model 1. The methods based on Performance Monitoring Coun- ters (PMCs) have been shown to be a good solution to es- timate power consumption. As a result, their applicability has been demonstrated on several fields such as power man- agement and application profiling. PMC-based power mod- els are used to perform live predictions of power behavior in order to guide power aware policies [2, 3, 4]. Moreover, they are also used in research for quickly exploring new ap- proaches since they allow to profile real systems and full executions of applications, avoiding the need of performing long-time and limited simulations [5]. In the end, they have been crucial in the process of addressing power issues. Modeling techniques to be embedded in a power man- agement framework demand three primary features: first, simplicity and systematic generation; second, a per architec- tural component decomposition of the overall estimate, so that the power management decisions can be accompanied by a real understanding of the observed performance levels; and finally, accuracy and responsiveness (see Figure 1). 2. TUTORIAL OVERVIEW The main topics covered in this tutorial are: • A systematic methodology for producing PMC-based power models on CMP architectures [4]. The method- ology ensures by definition the decomposability and 427