1 Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays Joey Wilson, Andrew Nelson, and Behrouz Farhang-Boroujeny joey.wilson@utah.edu, nelson@math.utah.edu, farhang@ece.utah.edu University of Utah & L-3 Communications Abstract—Modern implementations of discrete-time phase- locked loops (DT-PLLs) often contain delayed feedback. The delays are usually a side effect to pipelining, filtering, or other inner-loop mechanisms. Each delay increases the order of the system by introducing an additional pole to the closed-loop transfer function, and in many cases, makes the traditional type- 2 loop equations obsolete. This paper describes how the second- order notions of damping and natural frequency can be applied to type-2 DT-PLLs in the presence of any number of delays. It provides equations for loop parameters that will provide a desired transient behavior based on damping and natural frequency, along with a test to ensure the accuracy of the results. The novelty of this work is that loop parameters can be found in closed- form and ensured to be accurate, without the need for human interaction, simulations, or numerical root-finding algorithms. Index Terms—Phase locked loops, Delay effects, Reduced order systems, Dominant Poles I. I NTRODUCTION With the advent of the software radio and other modern digital devices, discrete-time phase-locked loops (DT-PLLs) are being implemented more than ever before. These modern implementations often contain delayed feedback, which is usually a side effect to pipelining, filtering, or other inner- loop mechanisms. Each sample delay introduces a pole into the closed-loop transfer function, resulting in a high-order system. The delays limit the loop’s stability regions, change its transient behavior, and in many cases render the traditional second-order analysis obsolete. It is not uncommon today to encounter loops with delays on the order of tens to hundreds. The effects of such delays on the stability and phase margin for DT-PLLs with delays have been previously investigated [1], [2], and [3]. The effect of delays on stability, root-locus, and frequency-response, and investigation of some specific scenarios with a low number of delays is covered in [4]. Other works have used optimization approaches to address the presence of delays. A Weiner approach to optimizing the loop filter in steady-state with the presence of delays is found in [5]. Previous work also showed that the type-II discrete- time PLL has the same structure as a Kalman filter, and a modified version has been proposed to compensate for loop delay [6]. A PLL designer is often concerned with finding loop param- eters K p and K i (as shown in Fig. 1) to achieve a particular transient behavior. Transient behavior is often described by the second-order notions of damping factor ζ and natural frequency ω n . [1], [2], and other references on DT-PLLs Fig. 1. Phase domain model of type-2 DT-PLL with PPI filter 20 40 60 80 100 120 140 160 180 200 0.5 1 1.5 Samples Amplitude Step Response: ζ =0.707, ω n T =0.05 No Delay D=10 Fig. 2. An example illustrating the inaccuracy of using traditional loop parameter equations in the presence of delays. Here, loop parameter values for Kp and K i are calculated from (2), regardless of the number of delays. use the following second-order definitions, regardless of the number of delays. ω n T =  K i and ζ = K p 2 √ K i (1) where T is the sample time interval. Equivalently, K p =2ω n Tζ and K i =(ω n T ) 2 . (2) The derivation of (1) can be found in [4]. Ignoring the delays often results in inaccurate prediction of transient behavior, especially at high ω n T values [7]. For example, using (2) to achieve a damping factor ζ = .707 and ω n T = .05 in the presence of 10 sample delays will yield loop parameters K p and K i that do not provide a response with the expected characteristics (See Fig. 2). Modern communication systems are designed to adapt their modulation, data rates, and other configurations under various conditions. With this flexibility comes the challenge of ensur- ing that loop parameters are accurate for proper tracking and signal acquisition. This is complicated further when delayed feedback is introduced, since stability regions are severely reduced. Even slight changes in loop parameters may become problematic in high-delay cases.