New Current Monitor Using Auto Zero Voltage Comparator for I DD Testing of Mixed-signal Circuits Vladislav Nagy, Viera StopjakovÆ Slovak University of Technology, Department of Microelectronics, Ilkovi7ova 3, 812 19 Bratislava, Slovakia, e-mail: vladislav.nagy@stuba.sk Abstract-An approach to the dynamic supply current sensing based on the measurement of voltage drop across a parasitic resistance of the supply voltage metal routing is presented. Auto- zero technique for voltage comparator offset cancellation, which provides very accurate and sensitive low voltage drop measurement is proposed. Therefore, one may use the proposed sensor as a current monitor for dynamic current testing of mixed- signal circuits without any additional element necessarily connected in series with the power supply line. The proposed current monitor was designed in a 0.35m CMOS technology. I. DESIGN OF THE CURRENT SENSOR In the last two decades, the supply current monitoring (I DD testing) has been used to supplement the conventional logic testing for many systems that require high quality test [1- 2]. I DD testing detects an abnormally increased or decreased supply current, caused by a fault present, flowing into the device under test (DUT). The main task of any current-based test method is sensing the current, which is drawn by the DUT using a sensing element with a minimal resistance in order to reduce the undesired power supply degradation [3-6]. We use a certain small parasitic resistance of a metal layer used in every chip to connect the supply voltage pad to the circuit core. This solution has no substantial influence on the DUT performance since there is no considerable voltage drop across the current sensor. To achieve low resistance of the sensing resistor the highest layer of metallization with the smallest sheet resistance is used. We employed the third metal layer (with sheet resistance of 50m:/฀) to implement the sensing resistor in the AMS 0.35Pm CMOS process. If we consider an acceptable serial resistance of 1: to sense the current, this implies the metal line of twenty squares. There is a very small voltage drop V do created by small supply currents from the range of hundreds of A to tenths of mA across this small serial resistance. In a standard CMOS technology, there is a problem to guarantee low input offset voltage in operational amplifiers. Since the magnitude of input voltage offset in CMOS technology may achieve hundreds of mV, it is necessary to use an offset compensation technique to reduce the input voltage offset. The auto-zero stabilization [7] is utilized in the current monitor proposed in this paper as a smart and efficient solution for dynamic reduction of the voltage comparator input offset. It also helps to compensate any other ineligible effects such as the offset drift (caused by temperature variations, ageing, mechanical stress, etc.) and flicker noise. The simple auto-zero topology is shown in Figure 1, where the voltage comparator has its input offset voltage V os . If the switches ) 1 are turned on, then the comparator is in unity-gain negative feedback loop configuration. This mode is called the offset cancellation phase. Then, the output voltage is expressed by the following equation: os os v v out V V A A V  #    1 (1) Thus, the offset voltage V os is stored on the capacitor C 1 with the opposite polarity, and in the next phase, when switches ) 1 are turned off and ) 2 are turned on, the voltage previously stored in C 1 is now in series with the regular offset voltage at the comparator input and they compensate each other. Problem with this topology is that switching the switch ) 2 at the comparator input disturbs the comparator output V comp . Hence, the undesired signal pulses are observed at the comparator output V comp , as shown in Figure 2 (lower curve). Fig. 1. Current sensor based on Auto-Zero comparator Therefore, additional switch ) 2 and capacitance C 2 are inserted at the output of the comparator, which eliminates the false defective supply current detection. When the switches ) 2 at the input are turned off, then the comparator output is also disconnected by the output switch ) 2 and the previous state of the output is stored on the capacitance C 2 . A simple invertor stage has been used as the buffer for minimal loading of this switch and capacitance C 2 . As a result, the current sensor output signal V buf is free of the undesired pulses due to working cycles of ) 2 input switches (Figure 2, upper curve). The proposed current monitor distinguishes between two states of the DUT. If the current flowing through the serial resistor R S produces a voltage drop V do higher then the reference voltage V ref , then the output is in its high state and DUT is defective. Low state of the current sensor output represents a nominal supply current expected in the fault-free 1-4244-0185-2/06/$20.00 c 2006 IEEE