Application of I DDT test towards increasing SRAM reliability in nanometer technologies Gábor Gyepes, Daniel Arbet, Juraj Brenkus and Viera Stopjaková Institute of Electronics and Photonics Faculty of Electrical Engineering and Information Technology Slovak University of Technology Bratislava, Slovakia gabor.gyepes@stuba.sk Abstract — Dynamic supply current test method (I DDT test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the I DDT waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of I DDT test in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated. Keywords – dynamic supply current, current test, open defects, SRAM, memory test, 6-transistor cell, I DDT , parametric test I. INTRODUCTION Testing of modern technology integrated circuits (ICs) is a great challenge of nowadays. Scaling of process technology has brought higher integration and thus, higher complexity too. However, as a consequence, with smaller dimensions and mass production, rises also the amount of possible defects and faulty pieces of circuits. Testing of logic ICs (e.g. SRAMs) mostly consists of logic tests based on fault models, which describe the effects of a present fault or defect on the logic function of the circuit. However, some defects like opens do not cause logic malfunction necessarily but rather degrade the reliability of the circuit. For the purpose of unveiling these defects another approach, parametric testing is used, where parameters like the static or dynamic current consumption, temperature, etc. are monitored. SRAMs are the most often used embedded memories, and in many cases, they may occupy more than 90 % of the total silicon in a system-on-chip (SoC) [1], [2]. Exhaustive functional tests are becoming too long because of the ever growing density (and thus, capacity) of memories, and test costs are already high. In the manufacturing process, the test expenses represent around 5-10 % for digital circuits, 10-30 % for mixed-signal ICs, and in the case of ICs with embedded radio frequency (RF) parts, test costs could reach even 50 % of the overall costs [3]. The presence of resistive opens is a very actual problem in recent technologies. Their probability has dramatically increased due to rapid increase of the number of interconnection layers and connections between them [4]. Moreover, opens are considered as hard detectable types of defects, which cannot be effectively unveiled by any functional test (unless considering full opens with “infinite” resistance). I DDT test could be the only parametric test method effectively unveiling resistive opens. It is worth to mention that I DDT testing becomes more effective in circuits of regular and uniform structures (e.g. memories), since I DDT current may be easier to sense and evaluate. Several test methods for covering open defects have been presented so far. In [5], a test approach using March test is presented, and a test technique based on design for testability is presented in [6]. Also some I DDT test methods were developed for detecting different types of faults. In [7], [8], [9] I DDT testing was discussed for covering stuck-at faults, coupling faults, transition faults and data retention faults. Efficiency of I DDT test regarding opens is discussed in [10], [11]. In [12], a current sensor for I DDT monitoring is presented, which distinguishes and evaluates the current peak value. The author’s previous research and achieved results are presented in [13], [14], [15]. The goal of this work is a comparison of I DDT efficiency in unveiling open defects resulted from monitoring characteristic parameters of the power supply current waveform for four SRAM arrays of cells with different cell ratio. After transforming the current to voltage, the efficiency resulted from monitoring the parameters of the voltage waveform is investigated. The SRAM circuits are implemented in a standard 90 nm CMOS technology, and the SRAM array consists of 64 6-transistor (6T) cells. II. BACKGROUND A. SRAM cell Dynamic supply current test has a greater efficiency in circuits with repeating structures, thus SRAMs are well suited for supply current testing [16]. The most common SRAM cell is the 6T CMOS implementation, which consists of two cross- coupled inverters formed by transistor complementary pairs M1-M3 and M2-M4, and by two access transistors M5 and M6 that are usually NMOS transistors, which ensure read and write access to the cell (Fig. 1) [2]. From all the SRAM cell types, the 6T cell is the most robust and typically, with low-power and low-voltage operation [2]. A fault-free SRAM cell draws no significant supply current in a steady state, which means quasi zero static current. Substantial supply current is only driven when the cell is changing its state. Under this condition, a temporary current path is induced between the voltage supply and ground. In combination with the charging and discharging of node capacitances, it causes a current flow for the time of the switching [9], which is called the dynamic or transient current. 978-1-4673-1188-5/12/$31.00 ©2012 IEEE