A New Look at Reversible Logic Implementation of Decimal Adder Rekha K. James, Shahana T K, K Poulose Jacob Sreela Sasi Cochin University of Science and Technology Gannon University Kochi, Kerala, India; Erie, PA, USA { rekhaj ames, shahanatk, kpj } (@/cusat.ac.in sasiOO I (&/gannon.edu Abstract - Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in [4] nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The using conventional reversible gates. In [4], a full adder design reduces the number of gates and garbage outputs design using two types of reversible gates - NG (New Gate) compared to the existing BCD adder reversible logic and NTG (New Toffoli Gate) with 2 garbage outputs was implementations. So, this design gives rise to an implemented. The BCD adder was then designed using such implementation with a reduced area and delay. full adders. Even though the implementation was improved in [5] using TSG reversible gates, this approach was not Keywords: BCD adder decimal arithmetic reversible logic taking care of the fanout restriction of reversible circuits, and hence it was only a near-reversible implementation. An improved reversible implementation of decimal adder with 1. INTRODUCTION reduced number of garbage outputs is proposed in [6]. The Ennis an important present work proposes a modified version of decimal Eonsidergyios dingw om itat . nr' addition using reversible gates which results in further consideration~ inlwpwrdgtldsg. Ladurs reduction in number of gates and garbage outputs with a principle states that a heat equivalent to kT*In2 iS generated reutoinumrofgesadabgeuptswha porinciplevstates tht af hefateqivalent losto kTere isgenerthe fanout of 1. The design is done using 3 types of reversible for every bit of information lost, where 'k' iS the gates Boltzmann's constant and 'T' is the temperature [1]. At gte so o room temperature, though the amount of heat generated may neessryabacgon on rever li as thatiareue besal t ano e eletd olwpoe dein.Th necessary background on reversible logic gates that are used be small it cannot be neglected for low p er dig e for the design is given. Then the proposed BCD adder is amount of energy dissipated in a system bears a direct ipeetduigrvril ae.Fnly h ae relaionsip t thenumbr ofbitserasd duing mplemented using reversible gates. Finally, the paper relputationshi Benneto the wenumber ofebitsr erased d urong wconcludes with a comparison of the proposed design with computation.Bowe t ene dationou ld different types of reversible BCD adders available in not ccurif te coputaion wer caried ut uing literature, in terms of delay, number of gates and garbage reversible circuits [2] since these circuits do not lose oututs. information. A reversible logic gate is an n-input, n-output outputs. (denoted as n*n) device that maps each possible input II. REVERSIBLE LOGIC GATES pattern to a unique output pattern. There is a significant difference in the synthesis of logic circuits using This section describes reversible gates that are used for conventional gates and reversible gates [3]. While the implementation of the proposed BCD adder. constructing reversible circuits with the help of reversible Figure 1 shows a 3*3 New Gate [7]. New Gate can be gates fan-out of each output must be 1 without feedback used as a gate that generates an AND gate, an OR gate or an loops. As the number of inputs and outputs are made equal XOR gate. If B='O', then Q=C and R=(A'C')± 1=A+C. there may be a number of unutilized outputs called garbage Similarly, when C='O', then Q=AB and R=A± B which are in erai reeribe iplmetaton. hisisth nube o the carry andl sum outputs of a half adder. Figure 2 shows a outputs added to make an n-input k-output function Feynman Gate [8]. Feynman Gate (FG) can be used as a reversible. For example, a single output function of 'n' variables~ ~ wilrqiea.es - graeotus lsia copying gate. Since a fanout greater than one iS not allowed, * ~~~this gate iS useful for duplication of the required outputs. 1-4244-1368-O/07/$25.OO ©C2007 IEEE