IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 12, DECEMBER 2007 3369 A Comprehensive Study of the Corner Effects in Pi-Gate MOSFETs Including Quantum Effects Francisco J. García Ruiz, Andrés Godoy, Francisco Gámiz, Senior Member, IEEE, Carlos Sampedro, and Luca Donetti Abstract—In this paper, simulation-based research on the elec- trostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs is car- ried out. To do so, a 2-D self-consistent Schrödinger–Poisson solver has been implemented. The inclusion of the quantum effects has been demonstrated to be necessary for the accurate simulation of these devices in the nanometer range. Specifically, this paper is focused on the corner effects in multiple-gate SOI MOSFETs, defined as the formation of independent channels with different threshold voltages. Corner effects are studied as a function of different parameters, such as the doping density, silicon-fin di- mensions, corner rounding, and gate oxide thickness. Finally, the relation between corner effects and the transition from a fully to a partially depleted body is analyzed. Index Terms—Corner effects, multiple-gate (MuG) MOSFETs, quantum effects, semiconductor-device modeling, silicon-on- insulator (SOI) technology. I. INTRODUCTION D URING THE last few decades, an extraordinary effort has been made to improve semiconductor-device features while reducing their dimensions. However, the miniaturization of traditional bulk CMOS transistors is reaching fundamental limits that, eventually, could slow down this trend. In or- der to follow the predictions of the International Technology Roadmap for Semiconductors [1], new materials and architec- tures have been proposed. Nonclassical silicon MOS structures, such as multiple-gate silicon-on-insulator (MuG SOI) MOSFETs (Fig. 1), have been proposed because of their ability to overcome several inherent limitations of bulk silicon technology, attaining higher speeds and reduced short-channel effects (SCEs). Double-gate SOI MOSFETs were introduced in early 1980s [2]. In these devices, the gates effectively control the energy barrier between the source and drain, and it has been demon- strated that the use of ultrathin silicon body is necessary to achieve improved short-channel characteristics. However, the fabrication of horizontal gate-channel-gate stacked structures is technologically quite challenging. A possible solution is to rotate this structure to a vertical one, producing a new device known as FinFET [3]. The FinFET can be modified when the top gate oxide thickness (Fig. 1) is reduced to the same value Manuscript received May 24, 2007; revised September 21, 2007. The review of this paper was arranged by Editor S. Datta. The authors are with the University of Granada, 18071 Granada, Spain (e-mail: franruiz@ugr.es). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.909206 Fig. 1. Cross section of different MuG SOI MOSFETs. as the lateral gates. The resulting device is known as trigate MOSFET. According to [4], the width-to-height ratio needed to maintain the body in full depletion is not so restricted as in the case of single or double-gate transistors. Trigate transistors on SOI substrate combine good subthresh- old characteristics with high on-currents and are considered to be very promising alternatives to planar devices in the sub- 50-nm gate-length regime. Improved versions of trigate SOI MOSFETs have been recently introduced in the literature. Among them, the Pi-gate [5] appears to be quite a promising device. Its geometry (Fig. 1) is part-way between trigate and gate-all-around (GAA) devices: The gate extends to some depth into the buried oxide, allowing a more effective control of the electrostatics in the channel region and shielding it from the electric-field lines originated in the drain [6]. A slightly modified version of the Pi-gate is the so-called Ω-gate, in which the buried gates get closer inside the oxide. When the silicon body is completely surrounded by the gate contact, the resulting structure is known as GAA [7]. Despite their benefits, when MuG devices are considered, new coupling effects appear due to their 3-D architecture [8]. Design studies of MuG SOI MOSFETs have revealed that the corners of the silicon body can significantly affect their I –V characteristics [4], [8], [9]. This phenomenon is commonly referred to as corner effects, and they are due to the formation of independent channels with different threshold voltages next to the corners (hereafter, corner regions) as compared to the sidewall gates. As will be shown next, under certain conditions, the corner components of the total current reflect a lower 0018-9383/$25.00 © 2007 IEEE