10.2-3 Abstract—This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively. I. INTRODUCTION With the increasing demand for consumer electronics (CE) devices that have a higher resolution, greater color depth, and higher refresh rate, the need for a scalable and high-speed interface has increased. The DisplayPort standard [1] is one of the high-speed serial interface technologies, which provides a scalable digital display interface for a broad range of applications such as PCs, TVs, projectors, and other CE devices. In addition, it provides optional support for audio transmission and content protection. The encoder and decoder of the DisplayPort physical layer are important blocks of the high-speed serial transmission. They provide link training symbol generation and detection, EMI reduction, symbol-level DC balancing, and a high transition density for the link clock phase tracking at the receiver. In this paper, we propose an efficient architecture of encoder and decoder for the DisplayPort physical layer. The resulting design can be easily applied to DisplayPort with low-cost hardware. II. DISPLAYPORT ARCHITECTURE Fig. 1 shows the overall transmitter and receiver architectures of DisplayPort. It is separated into two parts, the link and physical layers. The link layer provides isochronous transport services such as packing / unpacking, stuffing / unstuffing, and framing / unframing, and link and device management services such as discovering, configuring, and maintaining the link. The physical layer is responsible to transport the isochronous streams and secondary-data packets without a clock over a cable. It is further sub-divided into the digital encoder / decoder and analog transmitter / receiver sub-blocks, as shown in Fig. 1. The shaded blocks in Fig. 1 represent the proposed architecture of the encoder and decoder, which consists of data buffers, a data scrambler / de-scrambler, an interlane skewer / de-skewer, an ANSI 8B10B encoder / decoder, and so on. III. BUILDING BLOCKS A. Data scrambler and de-scrambler Fig. 2 shows the proposed data scrambler. It supports not only data scrambling, but also scrambler reset (SR) code insertion and interlane skewing. Data Buffer Parallel LFSR SR-code Selection Logic Counter Pattern Detector Multiplexer Multiplexer REG Data from Link Layer [15:8] Data to 8B10B Encoder REG REG REG REG REG 8 8 8 8 Fig. 2. Proposed data scrambler. The functions of SR code insertion and interlane skewing can be integrated in the link layer, but we designed them in the physical layer to alleviate the load on the link layer. Hence, we designed them so that they can be enabled or disabled. In order to increase the immunity of the link against external noise, the transmitter of DisplayPort must insert a skew of two clock cycles between adjacent lanes. It is designed to have 6 registers (REG) and a multiplexer. Every 512 th blank start (BS) symbol is replaced with an SR symbol to reset the linear feedback shift register (LFSR) of the An Efficient Architecture of Encoder and Decoder for DisplayPort Physical Layer Yongtae Kim, Junyoung Song, Woonhyung Heo, and Chulwoo Kim Advanced Integrated Systems Lab., Korea University, Seoul, Korea Link Training Pattern Gen. Data Scrambler Pre-emphasis ANSI 8B10B Encoder Interlane Skewer Data Buffer 10:1 Serializer Multiplexer Output Driver SR INS Symbol Lock Detector Data De-Scrambler Clock & Data Recovery ANSI 8B10B Decoder Interlane De-Skewer 1:10 De-Serializer Input Receiver De-Multiplexer Data Buffer Fig. 1. Overall transmitter and receiver architectures of DisplayPort. 978-1-4244-2559-4/09/$25.00 ©2009 IEEE