This work was supported by the project ΤΠΕ/ΠΛΗΡΟ/0308(ΒΕ)/07/SYSMANTIC, funded by the Cyprus Research Promotion Foundation. A Novel Prototyping and Evaluation Framework for NoC-based MPSoC K. Tatas 1 , K. Siozios 2 , A. Bartzas 2 , C. Kyriacou 1 and D. Soudris 2 1 Department of Computer Science and Engineering, Frederick University, Cyprus 2 School of Electrical and Computer Engineering, National Technical University of Athens, Greece ABSTRACT This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach. Keywords: NoC, FPGA, 3D chips, high-level exploration, NoC prototyping INTRODUCTION Future integrated systems will contain billion of transistors (Semiconductor Industry Association, 2011), composing tens to hundreds of IP cores. These systems will host emerging multimedia and network applications, should be able to deliver rich multimedia content and networking services. An efficient cooperation among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. An architecture being able to accommodate such a high number of cores, satisfying the needs for efficient communication and bandwidth, is the Network-on-Chip (NoC) (Benini & de Micheli, 2002; Jantch & Tenhunen, 2003). For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (implementations such as the AEthereal NoC (Kumar, A., Hansson, A., Huisken, J. & Corporaal, H., 2007) from Philips, the STNoC (STMicroelectronics, 2005) from STMicroelectronics and an 80-core NoC from Intel (Vangal, S. Howard, J., Ruhl, G.; Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S.,