A Flexible Network-on-Chip Simulator for Early Design Space Exploration Cristian Grecu, André Ivanov, Resve Saleh Department of Electrical and Computer Engineering University of British Columbia Vancouver, Canada Claudia Rusu, Lorena Anghel TIMA Laboratories Grenoble, France Partha P. Pande School of Electrical Engineering and Computer Science Washington State University Pullman, USA Vasile Nuca City Express Corp. Vancouver, Canada Abstract— The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators. Network-on-chip; simulator; performance; I. INTRODUCTION In recent years, the importance of on-chip interconnects has surpassed the importance of the transistors as a dominant factor of chip performance. The ITRS roadmap document [1] enumerates a number of technological challenges for interconnects and states that “technology alone cannot solve the on-chip global interconnect problem with current design methodologies”. The NoC design paradigm [2] is aimed at solving the global interconnect challenge for multi-core systems-on-chip through a shift in the design approach, where designers, rather than focusing mostly on the engineering of the computational cores with little concern for the inter-core wires, must employ structured, intelligent communication fabrics for transporting data across the chip. The use of NoCs as communication fabrics for multi- processor system-on-chip (MP-SoCs) raises many challenges that are actively investigated by the research community. Of major importance is the support of research with CAD tools that can allow rapid experimentation with multiple design options [3]. A distinct step in the overall NoC design flow is the communication architecture simulation, where a NoC is exercised against predefined requirements defined at different abstraction levels, from application level down to physical level. The level of abstraction at which data exchange is represented is extremely important for the nature and accuracy of design options that can be exercised and the information that can be extracted from the simulation. However, there is a gap in the data and hardware representation in existing simulation tools, between the low- level representations specific to RTL-level simulators, and high-level, transaction-based simulators. In this context, we present a simulation tool designed to bridge the gap between low- and high-level simulation approaches. It can be used independently or as a complement to other tools. The NoC simulator addresses the evaluation of NoC performance early in the design stage, without requiring a very detailed representation of the NoC under simulation, and allows comparison of different architectures and communication protocols in a uniform environment. The source code of this tool is publicly available and can be downloaded from http://www.ece.ubc.ca/~grecuc/simulator . II. RELATED WORK The need for simulation tools for the analysis and design of NoC architectures appeared concurrently with the proposal of NoCs as a viable solution for the global communication problem of large MP-SoCs. Due to the lack of dedicated software, researchers used communication networks simulators, such as ns-2 [4] and OPNET [5], which are relatively complex, difficult to configure and adapt for on-chip scenarios. The latter are targeted towards the simulation of very large networks with complicated protocols (i.e., TCP-IP and similar ones) and traffic models not representative for MP-SoC applications. The difficulties associated with using non-optimal tools have motivated research groups to develop a few dedicated NoC simulators. A major challenge when designing such tools is to achieve the right balance between the level of abstraction of data and NoC representation, and the accuracy of results and simulation speed. We can mainly differentiate two categories of NoC simulators, based on the granularity of data and hardware representation, both having their merits and advantages. The first category includes simulators that use a low-level representation of the NoC components and data. Zeferino et al. [6] have ported a parameterized VHDL model onto an FPGA