International Journal of Computer Applications (0975 – 8887) International Conference on Communication Technology 2013 35 Standby Leakage Power Reduction Techniques in Deep Sub-Micron CMOS VLSI Circuits Sangeeta Parshionikar P.G..Student and Assistant Professor Fr. Conceicao Rodrigues College of Engg. Mumbai University ABSTRACT The use of Very Large Scale Integration (VLSI) technologies in high performance computing, wireless communication and consumer electronics has been growing at a very fast rate. Every generation of VLSI technology reduces feature size of transistor and leads to more powerful and compact wireless devices. The challenge of the advanced VLSI technology is the increase in the leakage power consumption. In deep sub– micron technology, standby leakage power dissipation has emerged as major design considerations. Leakage control is very important, especially for low power applications and handheld devices such as cellular phones and PDAs. In this paper two techniques such as transistor stacking and sleepy transmission gate for reducing leakage power are proposed. In these techniques, the resistance of the path from Vdd to ground is increased, so that significant reduction in static power is achieved with small increase in delay. This work analyses the leakage power and delay of three basic digital circuits inverter, NAND and NOR gates and the same can extended to any complex digital implementation. The circuits are simulated with MOSFET models of level 54 in 90 nm, 45nm and 32nm process technology. General Terms Low-power VLSI design, Leakage power consumption Keywords Leakage power, static power, sleep transistor, threshold voltage, stacking. Process Technology 1. INTRODUCTION Development of low-power VLSI design is essential for current and future wireless devices. The advances in technology enable us to achieve higher density and performance at the same time results in increase in power consumption. In past day‟s technology the magnitude of leakage current was low and usually neglected. In current trends, the supply voltage is being scaled down to reduce dynamic power. The threshold voltages also follow the same scaling trend in order to satisfy the high speed requirements. This decrease of threshold voltages brings an exponential increase in sub-threshold currents [1]. Sub-threshold leakage is the weak inversion current between source and drain of MOS transistor observed when the gate voltage is less than the threshold voltage. Since the leakage current of the transistors determines the static power of a CMOS circuit, the increase in sub-threshold current increases the leakage power Deepak V. Bhoir, Ph.D Head of the Electronics Department Fr. Conceicao Rodrigues College of Engg. Mumbai University consumption of the circuit. Thus the total power consumption of the circuit is increased. Consequently, power dissipation is becoming recognized as a top priority issue for VLSI circuit design. Leakage power makes up to 50% of the total power consumption in today‟s high performance microprocessors [3]. Therefore leakage power reduction becomes the key to a low power design. Leakage power dissipation is the power dissipated by the circuit when it is in sleep mode or standby mode. Leakage power is given by equation 1 and the propagation delay (Tpd) of a circuit is given by equation 2. Pleak = Ileak * V dd (1) Tpd ∝ V dd / (V dd -V th ) 2 (2) Where Ileak is the leakage current that flows in a transistor when it is in off state, V dd is the supply voltage, Vth is the threshold voltage of the transistor. This power dominates dynamic power especially in deep submicron circuits and also in circuits that remains in idle mode for a long time such as cell phones. In all such applications, it is important to prolong the battery life as much as possible and now with growing trend towards portable computing and wireless communication, power dissipation has become one of most critical factor in continued development of micro-electronic technology. Therefore the focus is on the reduction of leakage power dissipation. The rest of the paper is organized as follows, a review of the related work is presented, in Section 2. In Section 3, the proposed work on a leakage reduction for combinational CMOS logic gates is presented, which is followed by the simulation results and conclusions in Sections 4 and 5, respectively. 2. RELATED WORK High leakage current in deep-submicron technology is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. This section reviews different approaches for leakage current reduction techniques. All these techniques are effective in reducing leakage power and ultimately all come down to a fundamental set of concepts: dissipation is reduced by lowering supply voltage, voltage swing, physical capacitance, switching activity or by introduction of a high resistance path between VDD and ground. In self-adjustable voltage level circuit, the output voltage of the circuit is applied to any load circuit [3]. During the active mode