A Test Chip for Automatic MOSFET Mismatch Characterization H. Klimach Universidade Federal de Santa Catarina Florianópolis - Brazil +55 48 33317720 klimach@eel.usfc.br M. C. Schneider Universidade Federal de Santa Catarina Florianópolis - Brazil +55 48 33317720 marcio@eel.ufsc.br C. Galup-Montoro Universidade Federal de Santa Catarina Florianópolis - Brazil +55 48 33317720 carlos@eel.ufsc.br ABSTRACT This paper describes a test circuit for intensive characterization of MOS transistors mismatch. It aggregates analog switches, a shift register and a reference circuit, as well as the matrix of 1296 transistors to be tested. This circuit was integrated in a 0.35 μm bulk technology, and was designed to give experimental support for our MOSFET mismatch model. The test chip was characterized over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, allowing the analysis of MOSFET mismatch from bias, process and geometric parameters. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Measurement, Performance, Experimentation. Keywords MOSFET, analog design, matching, mismatch, characterization. 1. INTRODUCTION Mismatch is the denomination of time-independent variations between identically designed components [1], [2]. The performance of most analog or even digital circuits relies on the concept of matched behavior between identically designed devices. In analog circuits, the spread in the dc characteristics of supposedly matched transistors results in inaccurate or even anomalous circuit behavior. Also, for digital circuits, transistors mismatch leads to propagation delays whose spread can be of the order of several gate delays for deep-submicron technologies [3]. The shrinkage of the MOSFET dimensions and the decreasing in the supply voltage make matching limitations even more important in today advanced processes [4]. Stochastic nature of local mismatch of MOS transistors makes its electrical characterization a complex, time consuming (and boring) task. A large number of samples, having different geometries, must be measured under a wide range of bias conditions, as a way to characterize device behavior and extract statistical model parameters. Traditional design of test structures for mismatch characterization is based on grouping the transistors in an n- dimensional matrix, as a way to share the limited number of output pads. So, similar transistors are joined in common-drain (or source, or gate, or even bulk) arrays, and individually measured by selective bias applied to a specific combination of pads. In this way, for example, it is possible to have 200 transistors, divided in 5 arrays of 20 devices with the same Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. SBCCI’06, August 28 – September 1, 2006, Minas Gerais, Brazil. Copyright 2006 ACM 1-59593-479-0/06/0008...$5.00. Figure 1. Microphotograph of the test chip (fabricated in the TSMC 0.35 μm process, on a 28-pad 1.5 mm square chip). The two rectangular large areas are the NMOS (down) and the PMOS (up) transistor arrays. Between them is part of the serial register (36 bits) and the selection switches. At the right side of the die is the final part of the serial register (45 bits) and the reference transistors for biasing. 83