ICSE'96 Proc., Nov. 1996, Penang, Malaysia 26 zy 1 Test Processor ASIC Design Md. Liakot Ali, Zahari Mohamed Darus, Mohd. Alauddin Mohd. Ali Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Malaysia Iftekhar Ahmed Faculty of Computer Science and Information Technology University of Malaya, Malaysia Abstract In this paper, a design of a Test Processor ASIC employing probabilistic approach is presented. The test processor chip is computer programmable. It consists of linear feedback shift register (LFSR) which can select one of 16 polynomials and set user programmable seed for every test set, signature analyzer and 3 built-in RAMS and other control circuitry. It is capable of generating random numbers and apply them to the circuit under test (CUT) and then retrieve the responses from the CUT. It can generate signature by compressing the response data and detect circuit faults by comparing this signature with that of a good CUT. This ASIC can be used to design low cost IC tester of reliable performance. Keywords: Test Processor, CUT, LFSR, BIST, ASIC, PRV. Lntroduction Different techniques are followed for hardware test pattern generation as deterministic testing, pseudorandom testing, weighted random testing and mixed mode testing. They offer different advantages and trade offs between the test data storage, test application time, hardware overhead and fault coverage. Deterministic test generation of test vectors to detect possible faults reliably is extremely difficult. Automatic Testing Equipments (ATEs) are usually employed to generate test vectors, apply them to CUT input pins and compare the output responses with the expected responses. Main disadv'antages of ATEs are high cost and slow test speed. As an altemative to deterministic vectors, pseudorandom (PR) vectors have been employed esciently to test ICs. Linear feedback shift registers (LFSRs) are commonly 'used as PR vector generator [l]. Recently Cellular Automata (CA) based PRVG have been proposed as an alternative to LFSR and it has been shown that PR vectors generated by CA register have improved randomness and they are less correlated than those of LFSR zy [2]. Previous researchers have shown that better randomness and less correlation in the PR sequence result in better fault detection capability [3]. In 1980s, emphasis has been given on weighting PR to improve performance of probabilistic testing. Biasing or weighting equiprobable PRVs to near 1 or 0 can provide improved fault coverage of PR resistant circuit with a smaller number of PRVs [4, 5, 61. Later on, Koenemann [7] proposed a very attractive technique for encoding test data based on intelligent reseeding of single polynomial LFSR. This technique is compatible with scan and offers reduced storage requirements, shorter test application time and smaller area overhead compared to weighted random patterns. Further on, a more improved technique for the encoding scheme based on reseeding of Multiple Polynomial LFSR has been proposed [8, 91. This paper presents the design and simulation results of an ASIC based on this idea for external testing of VLSI circuit Design of Test Processor Figure 1 below shows the main component of the Test Processor. zyxw 0 -7803 - 3388 - 8/96/$5.00 01996 IEEE