PATHWAYS FOR ADVANCED TRANSISTORS USING HAFNIUM – BASED OXIDES BY ATOMIC LAYER DEPOSITION Ana R. Londergan, Sasangan Ramanathan, Jereld Winkler Tom E. Seidel Genus, Inc. 1139 Karlstad Drive, Sunnyvale CA, 94089 Jim Gutt, George Brown, Robert W. Murto International Sematech 2706 Montopolis Drive, Austin, TX 78741-6499 The main challenge facing the gate stack community today is the continuous scaling of high- performance devices (target: EOT ≤ 1 nm, Jg ≤ 1 A/cm 2 and mobility approaching that of SiO 2 ), where there are no known solutions [1]. The focus is on Hf -based materials, including silicates, aluminates, and quaternary alloys, such as Hf-Si-O-N, and Hf-Al-O-N where the goal is to demonstrate an acceptable trade-off between dielectric constant and thermal stability. Additionally, the interface to Si needs to be carefully optimized to simultaneously achieve high mobility and low EOT values. Atomic layer deposition (ALD) has generated a lot of interest for the growth of the high k-oxide due to the many benefits inherently offered by this technology [2]. There is an increasing number of publications showing leading edge work in the gate area using ALD to deposit Hf -based oxides and laminates [3-5]. At Genus, ALD was developed on a commercially established LYNX 2 platform and subsequently scaled to 300 mm wafers on LYNX 3. Flexibility built into the hardware and software allows the engineering of interfaces and complex alloy and nanolaminate structures with high precision, reliability, and competitive throughput. Using the variation of thickness deposition rate per cycle as a metric, the variance with respect to process temperature, process pressure, pulse timings and purge timings have indicated an overall control capability on the order or less than 1% for Al 2 O 3 and HfO 2 [6]. This process control is confirmed by the excellent leakage distributions reported in this presentation. Additionally, good composition control for the hafnium aluminates is established. Good trade-off between thermal stability and dielectric constant can be realized for 30 – 50 mol. % Al 2 O 3 , with favorable band offset values for low leakage [6, 7]. This presentation will review our current results on integration of ALD deposited Hf-based oxides in advanced transistors. As the interface between the Si and the high-k dielectric is of foremost importance for device performance, methods for surface treatment prior to the oxide deposition will be addressed. For example, the probability distribution of gate leakage in NMOS devices fabricated from 30 and 40 Å thick ALD HfO 2 layers with NH 3 and O 3 – based pre-treatment are shown in Figures 1 and 2, respectively. Both pre-treatments were carried out ex-situ. The results from SiO 2 – based devices are included for reference in both figures. Tight leakage distribution in the HfO 2 transistors is evidenced in both cases and the NH 3 – based pre-treatment yielded slightly lower leakage. Excellent Idsat and g m with large overdrive were measured on these devices. Additionally, the impact of the post deposition anneal (PDA) on leakage, EOT and mobility will be reviewed. Special attention is given to the trade-off between EOT and mobility presented by PDAs with and without oxygen containing ambient gases. Results from PMOS and NMOS devices will be compared and discussed with respect to integration differences and potential impact of B penetration. References: 1. H. R. Huff, G. A. Brown, L. A. Larson and R. W. Murto, ECS Conf. Proc., March 2001. 2. Atomic Layer Deposition, AVS Topical Conference, May 2001 and August 2002, Presentations. 3. J.H. Lee, Y.S. Kim, H.S. Jung, J.H. Lee, N.I. Lee, H.K. Kang, J.H. Ku, H.S. Kang, Y.K. Kim, K.H. Cho, and K.P. Suh, VLSI Digest of Tech. Papers, IEEE Cat. No. 01CH37303, 9.2, p. 84, 2002. 4. E. P. Gusev, et. al., IEDM Conf. Proc., IEEE, 2001. 5. J.M. Hergenrother, et. al., IEDM Conf. Proc., IEEE, 2001. 6. A. R. Londergan, S. Ramanathan, K. Vu, S. Rassiga, R. Hiznay, J. Winkler, H. Velasco, L. Matthysse and T. E. Seidel, C. H. Ang, H. Y. Yu and M. F. Li, ECS Conf. Proc,. Vol. 2002-11, p.163, 2002. 7. H.Y. Yu, et. al., Appl. Phys. Lett., 81, No. 2, 2002. NH3 HO 30A 600C NH3 HO 30A 700C NH3 HO 30A N2O ( NH3 HO 40A 600C NH3 HO 40A 700C NH3 HO 40A N2O ( SiO2 (21A) (1w) 20x20um Gate Leakage Units (LOGA) -4 -5 -6 -7 -8 -9 -10 Probability Distribution (%) 100 90 80 70 60 50 40 30 20 10 0 Figure 1 Probability distribution of gate leakage in NMOS devices fabricated from 30 and 40 Å thick ALD HfO 2 layers with NH 3 – based pre-treatment. O3 HO 30A 600C O3 HO 30A 700C O3 HO 30A N2O ( O3 HO 40A 600C O3 HO 40A 700C O3 HO 40A N2O ( SiO2 (21A) (1w) 20x20um Gate Leakage Units (LOGA) -4 -5 -6 -7 -8 -9 -10 Probability Distribution (%) 100 90 80 70 60 50 40 30 20 10 0 Figure 2 Probability distribution of gate leakage in NMOS devices fabricated from 30 and 40 Å thick ALD HfO 2 layers with O 3 – based pre-treatment.