Analog Integrated Circuits and Signal Processing, 26, 7±16, 2000 # 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. An Analog Correlator for a WCDMA Receiver M. NEITOLA AND T. RAHKONEN Department of Electrical Engineering and Infotech Oulu, University of Oulu, 90571 Oulu, Finland E-mail: marko.neitola@ee.oulu.® Received February 14, 2000; Revised June 13, 2000; Accepted June 13, 2000 Abstract. A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (®ngers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a ®rst-order low-pass continuous-time oversampling sigma±delta analog-to- digital converter and a second-order sinc type of decimation ®lter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8±512 depending of the PN code length. The circuit was implemented in 0.8 mm CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 mm 6 686 mm and the current drain is approximately 370 mA. Key Words: analog correlator, WCDMA receiver, continuous-time sigma±delta modulator 1. Introduction In CDMA (code division multiple access) systems the transmitted signal is multiplied by a spreading code, which widens the spectrum and makes the system more tolerant to interferenceÐto such extent that several users can share the same frequency band. In the receiver, the data is collected again by synchro- nously multiplying the input signal with the same spreading code. Typically, this is done digitally after sampling the input signal at a rate of 2 or 4 times the chip rate. WCDMA (wideband CDMA) is designed to support a variety of data services from low up to 2 Mb/s bit rates and it differs from the present IS-95 CDMA standard mostly by bandwidth. The channel spacing is 5 MHz and the signal is QPSK or BPSK modulated at a chip rate of 3.84 MHz. Hence, at baseband, A/D converters capable for 16 MS/s sampling frequency are needed, and those tend to consume tens of mW of power. Here, an analog correlator is described that provides complex correla- tion and A/D conversion with merely 1 mW. Several analog solutions for correlating receivers exist. SAW ®lters are passive and lower power devices, but unfortunately have ®xed response. CCD delay lines are promoted in Hahm et al. [1], estimating 7 mW dissipation for a 128 tap FIR, but the dissipation increases steeper than linearly with the length of the ®lter. A delay line made of cascaded active S/H stages was used in Shibano et al. [2], where a 128-tap, 120 mW, 50 MS/s FIR was built. A passive 128 MS/s, 64-chip, 75 mW correlator with A/D converters was built in Onodera and Gray [3], but the required area and power dissipation are quite high. 2. The Correlator Structure Fig. 1(a) illustrates the spectrum of the input CDMA signal consisting of several transmissions, all coded with separate codes. In Fig. 1(b), after synchronous analog multiplication with the correct de-spreading code the desired signal is narrowband while the information of other code channels is still wideband. Therefore, in order to avoid adjacent channel aliasing the sampling rate must be large even though the signal bandwidth is narrow. This ®ts well with sigma±delta (SD) A/D converters that employ high oversampling rate to shape the otherwise high quantization noise and to relax anti-alias require- ments. Thus, by moving the correlation into analog domain, SD converters commonly used in narrow- band receivers can again be used instead of power-