Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin Techniques of Informatics and Microelectronics for Computer Architecture Laboratory (TIMA) 46 Avenue Felix Viallet, 38030 Grenoble, France {Bertrand.Folco, Vivian.Bregier}@imag.fr WWW home page: http://www.tima.imag.fr/cis in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but do not perform well to automatically synthesize and optimize. This paper presents a new methodology to model and synthesize data path QDI circuits. The model used to represent circuits is based on Multi-valued Decision Diagrams and allows obtaining QDI circuits with two-input gates. Optimization is achieved by applying a technology mapping algorithm with a library of asynchronous standard cells called TAL. This work is a part of the back-end of our synthesis flow from high level language. Throughout the paper, a digit-slice radix 4 ALU is used as an example to illustrate the methodology and show the results. 1 Introduction Asynchronous circuits do not have a global signal to synchronize them. Synchronization between blocks is locally done. Those circuits show very interesting reusability, etc [1]. This work is part of the TAST [2, 3] (Tima Asynchronous Synthesis Tool) independently of delays in gates and wires, apart from the assumption that some forks are isochronic. This kind of asynchronous circuit is particularly robust. But robustness has a cost; these circuits usually have more transistors than the others, especially when standard cells are targeted. Many efforts are directed towards circuit TAST are quasi-delay insensitive (or QDI [4]). QDI circuits are functionally correct properties such as low power consumption, noise emission, security, robustness, Abstract. Quasi delay insensitive circuits are functionally independent of delays asynchronous tools similar to synchronous ones. Today, to adopt the asynchronous technology the industry needs powerful Folco, B., Brégier, V., Fesquet, L., Renaudin, M., 2007, in IFIP International Federation for Information project, aimed at developing and prototyping such tools. The synthesized circuits in Processing, Volume 240, VLSI-SoC: From Systems to Silicon, eds. Reis, R., Osseiran, A., Pfleiderer, H-J., (Boston: Springer), pp. 55–69.