972 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 12, DECEMBER 2006 Plasma-Induced Damage in High-k /Metal Gate Stack Dry Etch Muhammad Mustafa Hussain, Seung-Chul Song, Senior Member, IEEE, Joel Barnett, Chang Yong Kang, Gabe Gebara, Barry Sassman, and Naim Moumen Abstract—Plasma-based dry etch is used as the industry stan- dard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replac- ing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their al- loys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution. Index Terms—Gate-induced drain leakage (GIDL), high-k/ metal gate, plasma dry etch, threshold-voltage, wet etch. I. I NTRODUCTION P LASMA processes in the fabrication of advanced CMOS devices have become increasingly difficult as a result of the introduction of new materials in conjunction with di- minished feature dimensions. For ultralarge scale integrated devices, plasma processes are widely employed to transfer shrinking feature sizes successfully. However, plasma-induced charging damage has been found to degrade the electrical characteristics and reliability of the gate dielectric [1]–[7]. The effect of such damage on the wafer and, consequently, on the device depends on the type of surface or material that is exposed to the plasma. The damage arises due to: 1) bom- bardment by high energy particles; 2) unwanted chemical reac- tions; 3) creation of electron–hole pairs due to ultraviolet light; 4) deposition and subsequent permeation of impurities; and 5) plasma-dry-etch-induced gaseous or ionized charge deposi- tion in the dielectric film [8]. These conclusions were drawn using polysilicon gate over silicon dioxide dielectric film. A study was needed to investigate the impact of plasma- induced damage on high-k/metal gate stack devices. Devel- oping a halogen-based dry etch chemistry to etch new metal gates and their alloys is extremely difficult. In dual metal gate CMOS, the presence of two different metals, perhaps of dif- Manuscript received July 7, 2006; revised September 29, 2006. The review of this letter was arranged by Editor C. Chang. M. M. Hussain, S.-C. Song, J. Barnett, C. Y. Kang, and B. Sassman are with SEMATECH, Austin, TX 78741 USA (e-mail: Muhammad. Hussain@sematech.org). G. Gebara is with the Advanced Technology Development Facility, Austin, TX 78741 USA. N. Moumen is with IBM, Hopewell Junction, NY 12533 USA. Color versions of Figs. 2–4 are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2006.886327 Fig. 1. Gate etch of a TaSiN nMOSFET. ferent thicknesses, makes this task more complicated [9], [10]. Therefore, there was an interest to compare the device perfor- mance between dry-etched and wet-etched high-k/metal gate stack. Since the wet etch module largely depends on weak chemistries and the module can etch every current candidate metal with high selectivity over high-k dielectric films, the wet etch could be easily implemented for the gate etch for demonstration or research purpose. II. EXPERIMENTAL A 10-nm tantalum silicon nitride (TaSiN) nMOSFET was fabricated on a 2.5-nm hafnium oxide (HfO 2 ) dielectric film. TaSiN was deposited by physical vapor deposition, and HfO 2 was deposited by atomic layer deposition [11]. A titanium nitride (TiN) nMOSFET was used as a standard reference. Splits were made so that the metal gates were etched after the standard polysilicon cap dry etch with either the standard dry etch or the developed wet etch module. A significant impact was seen in the gate leakage current and gate-induced drain leakage (GIDL) current (this belongs to Section III). A trans- mission electron microscope (TEM) was used to physically study the fabricated devices (Fig. 1). III. RESULTS AND DISCUSSIONS The threshold-voltage V t is the most sensitive parameter for oxide charging and interface damage. Fig. 2 gives the distribu- tion of the threshold-voltage V t . From the distribution curve, it can be seen that wet-etched gate stack nMOSFET has confined the threshold-voltage V t distribution. However, in the case of plasma-based dry-etched gate stack nMOSFET, wide distrib- ution of threshold-voltage V t , especially toward the positive direction, is observed. This shift can be attributed to classi- cal charging damage during the plasma etching process [12]. 0741-3106/$20.00 © 2006 IEEE