A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling Mohsen Radfar ⇑ , Jack Singh Department of Electronic Engineering, La Trobe University, Melbourne, Victoria 3086, Australia article info Article history: Received 19 February 2014 Received in revised form 26 June 2014 Accepted 18 July 2014 Available online xxxx Keywords: Timing yield Subthreshold design Forward body biasing Process Temperature Voltage variations abstract Drastic yield reduction at sub/nearthreshold voltage domains, caused by the severe process, voltage, and temperature (PVT) variations in this region, is challenging characteristic of recent nanometre sensory chips. Using a variation sensitive and ultra-low-power design, this paper proposes a novel technique capable of sensing and responding to PVT variations by providing an appropriate forward body bias (FBB) so that the delay variations and timing yield of whole system as well as energy-delay product (EDP) are improved. Theoretical analysis for the error probability, confirmed by post-layout HSPICE simulations for an 8-bit Kogge–Stone adder and also two large Fast Fourier Transform (FFT) processors, shows considerable improvements in severe PVT variations and extreme voltage scaling. For this adder, for example, the proposed technique can reduce error rate from 50% to 1% at 0.4 V. In another implemen- tation, in average 7 delay variation and 4 EDP improvement is gained after this technique is applied to an iterative 1024pt, radix 4, complex FFT while working in sub/nearthreshold voltage region of 0.3 V–0.6 V. Also, pipelined version of the FFT consumed only 412pJ/FFT at 0.4 V while processing 125 K FFT/sec. Ó 2014 Elsevier Ltd. All rights reserved. 1. Introduction With the introduction of 65 nm technologies, reliability of circuits started to challenge the transistor scaling which is an essential trend for continuation of performance, area and energy improvements in silicon chips fabricated for sensory systems. Increasing defects in fabrication process as a result of aggressive transistor scaling is the source of this unreliability which reduces manufacturing yield. As it will be seen, the final yield for ultra- low power circuits depends on reliability (or resilience to temper- ature variation and voltage noise) and satisfying the performance and energy goals which are all correlated, and if not met, the specific die will be discarded. These challenges are pronounced even more seriously at the subthreshold voltages, from which low energy wireless applications benefit the most by trying to min- imize the power use for a given performance requirement [1]. As PVT variations rise exponentially with the voltage scaling, this results in a dramatic uncertainty and still urges designers to employ adaptive body-bias (ABB) techniques [2] despite the fact that technology scaling counteracts the body biasing effect (with the increase of dopants in the below 100 nm device channels to cause stronger inversion). Although efficient in the superthreshold region, the impact of the body biasing is especially sensed at the subthreshold voltages because of the exponential increase in the sensitivity of devices to the threshold voltage. For example in a typical 90 nm technol- ogy, if threshold voltage is changed by 50 mV at a 1 V supply volt- age, delay varies 13% whereas it results in a 55% delay increase at a 0.45 V supply voltage [3]. As mentioned, susceptibility to noise or voltage variations is a major source of performance failure at subthreshold voltages. Because threshold voltage (V TH ) is managed by an independent doping process, V TH in PMOS and NMOS devices can be different considerably. This, for example, can result in an insufficient high output voltage at the fast NMOS slow PMOS corner (in which NMOS devices are much leakier than PMOS ones) or an insufficient low output voltage at a fast PMOS slow NMOS corner. Conse- quently, not only noise margins can be violated at process corners, but also either rising or falling time is extremely long which in return results in increased timing breaches. As PMOS and NMOS transistors can be controlled independently using body biasing techniques, this opens many opportunities for designers to optimally tune the b-ratio and preventing V TH mis- match problems. For example, authors in [4] used V TH balancing http://dx.doi.org/10.1016/j.microrel.2014.07.138 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved. ⇑ Corresponding author. Tel.: +61 394793210. E-mail address: m.radfar@latrobe.edu.au (M. Radfar). Microelectronics Reliability xxx (2014) xxx–xxx Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Please cite this article in press as: Radfar M, Singh J. A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.07.138