Hindawi Publishing Corporation Journal of Electrical and Computer Engineering Volume 2012, Article ID 358281, 2 pages doi:10.1155/2012/358281 Editorial ESL Design Methodology Deming Chen, 1 Kiyoung Choi, 2 Philippe Coussy, 3 Yuan Xie, 4 and Zhiru Zhang 5 1 Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA 2 School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea 3 Department of Sciences and Techniques, Lab-STICC, Universit´ e de Bretagne-Sud, Lorient 56321, Cedex, France 4 Department of Computer Science and Engineering, Pennsylvania State University at University Park, University Park, PA 16802-1294, USA 5 High-level Synthesis Department, Xilinx Inc., San Jose, CA 95124, USA Correspondence should be addressed to Deming Chen, dchen@illinois.edu Received 15 May 2012; Accepted 15 May 2012 Copyright © 2012 Deming Chen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1. Introduction ESL (electronic system level) design is an emerging design methodology that allows designers to work at higher levels of abstraction than typically supported by register transfer level (RTL) descriptions. Its growth has been driven by the continuing complexity of IC design, which has made RTL implementation less efficient. ESL methodologies hold the promise of dramatically improving design productivity by accepting designs written in high-level languages such as C, System C, C++, and MATLAB, and so forth, and implementing the function straight into hardware. Designers can also leverage ESL to optimize performance and power by converting compute intensive functions into customized cores in System-on-Chip (SoC) designs or FPGAs. It can also support early embedded- software development, architectural modeling, and func- tional verification. ESL has been predicted to grow in both user base and rev- enue steadily in the coming decade. Meanwhile, the design challenges in ESL remain. Some important research chal- lenges include effective hardware/software partitioning and co-design, high-quality high-level synthesis, seamless system IP integration, accurate and fast performance/power model- ing, and efficient debugging and verification, and so forth. With the invitation of Journal of Electrical and Computer Engineering of the Hindawi Publishing Corporation, we started the effort of putting together a special issue on ESL design methodology. After call for papers, we received sub- missions from around the globe, and after a careful review and selection procedure, eight papers are accepted into this special issue. These papers cover a wide range of important topics for ESL with rich content and compelling experimen- tal results. We introduce the summaries of these papers next. They are categorized into four sections: high-level synthesis, modeling, processor synthesis and hardware/software co- design, and design for error resilience. 2. High-Level Synthesis In the paper “Parametric yield-driven resource binding in- high-level synthesis with multi-Vth/Vdd library and device sizing” Y. Chen et al. demonstrated that the increasing impact of process variability on circuit performance and power requires the employment of statistical approaches in analyses and optimizations at all levels of design abstractions. This paper presents a variation-aware high-level synthesis method that integrates resource sharing with Vth/Vdd selection and device sizing to effectively reduce the power consumption under given timing yield constraint. Experimental results demonstrate significant power yield improvement over con- ventional worst-case deterministic techniques. D. Menard et al. present in the paper “High-level synthesis under fixed-point accuracy constraint ” a new method to integrate high level synthesis (HLS) and word-length opti- misation (WLO). The proposed WLO approach is based on analytical fixed-point analysis to reduce the implementation cost of signal processing applications. Authors demonstrate that area savings can be obtained by iteratively performing WLO and HLS, in the case of a latency constrained applica- tion, by taking advantage of the interactions between these two processes.