VHDL Description of a Synthetizable and Reconfigurable Real-Time Stereo Vision Processor CARLOS CUADRADO AITZOL ZULOAGA JOS ´ E L. MART ´ IN JES ´ US L ´ AZARO JAIME JIM ´ ENEZ Dept. of Electronics and Telecommunications University of the Basque Country Alda. Urquijo S/N, 48013 Bilbao SPAIN Abstract: - This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigura- bility, the hardware requirements are optimized for different image resolutions and matching scenarios. To have a configurable description of a stereo processor provides the entity to design hardware stereo matching systems, imple- menting by incremental design disparity consistence algorithms, multi-stereo correlations or multi-scale algorithms. The results of the hardware synthesis of this code have being implemented in several reconfigurable devices. We show the results of the synthesis and its implementation cost in logic elements and delays. Key-Words: - Stereo Vision, Real-Time, VHDL, Reconfigurable Logic, FPGA, SoC 1 Introduction Computational stereo vision for extraction of three- dimensional scene structure has been an intense area of research in the last decade [1]. In this time, significant improvements have been carried out in the development of the stereo matching algorithms and their digital im- plementations [2, 3, 4]. Although the digital stereo vision is a mature disci- pline, the matching problem is still a very expensive computational task. In addition, no general solution ex- its to the matching problem and several approach have being used in order to optimize the unreliable matches due to occlusions, photometric distortions or camera noise [5, 6]. In many applications it needs recovery the three- dimensional structure of the environment at video-rate. The digital stereo vision is a useful solution for these applications when it is not possible to use active light systems. The researchers have applied the stereo vision to robotics autonomous navigation, people and object tracking, gaming and telepresence applications [7], and others. Actually a main target of the digital stereo vi- sion is to reduce the size, the cost and the power re- quirements to employ this technique in small and au- tonomous applications. For real-time stereo vision applications it needs to ap- peal to specific and extensive parallel hardware. The real-time implementations use of special purpose hard- ware, like arrays of Digital Signal Processors (DSP) [8] or several Field Programmable Gate Arrays (FPGA) [9]. In the last years, some implementations of the real-time stereo vision algorithms have used general- purpose microprocessors [4] with a relative success. The major advantages of the design on FPGA are the low cost of prototype and the fast design cycle. FPGA implementations allow to exploit the parallelism and the pipeline usual in vision algorithms. In addition, we can generate high specific and parameterizable hardware. The growing of the logic elements and capabilities embedded in the programmable logic devices make possible to implement a complex video-rate stereo vi- sion system. The reconfigurable logic also allows to use the same hardware device for vision and non-vision sys- tems, modulating, through a parameterizable descrip- tion, the hardware resources dedicate to the vision al- gorithms. In this paper we propose the implementation of a Real-Time Stereo Vision Processor (RTSVP) on a re- configurable logic device using VHDL hardware de- scription language. The VHDL description provides the capacity of generate high specific and optimize hard- ware. Every logic blocks of the RTSVP are tunable in order to adjust the hardware used by the stereo vision al- gorithm and the necessities of a specific practical appli-