Short-Channel Poly-Si Thin-Film Transistors with Ultrathin Channel and Self-Aligned Tungsten-Clad SourceÕDrain Hsiao-Wen Zan, a Ting-Chang Chang, b, * ,z Po-Sheng Shih, c Du-Zen Peng, c Po-Yi Kuo, c Tiao-Yuan Huang, c Chun-Yen Chang, c and Po-Tsun Liu d a Institute of Electro-Optical Engineering, c Institute of Electronics, National Chiao Tung University, Taiwan b Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan d National Nano Device Laboratory, Hsin-Chu 300, Taiwan A short-channel polycrystalline silicon poly-Si thin-film transistor ( W/ L = 10 m/3 m) with an ultrathin channel 30 nm and self-aligned tungsten-clad source/drain structure is demonstrated. With WF 6 and SiH 4 gas flow ratio of 40/12, selectively deposited tungsten film over 100 nm thick can be easily grown on source/drain regions. As a result, the parasitic source/drain resistance is greatly reduced, leading to improvement of device driving ability. Because tungsten deposition can be carried out at a low processing temperature of 300°C, the proposed simple structure is compatible with conventional top-gate structure and can be readily applied to low-temperature poly-Si fabrication. © 2003 The Electrochemical Society. DOI: 10.1149/1.1635093 All rights reserved. Manuscript received March 3, 2003. Available electronically December 15, 2003. Recently, polycrystalline silicon poly-Si thin-film transistors TFTs have been attractive as applications in peripheral circuits for active matrix liquid-crystal displays AMLCDs. 1 To achieve higher speed and circuit densities, it is necessary to scale down device dimensions. However, short-channel poly-Si TFTs suffer from se- vere kink effect due to the presence of a floating body. Specifically, holes generated by impact ionization accumulate in the body and raise its potential, which turns on the parasitic bipolar junction tran- sistor BJT. 2 Minimizing the body region by using a thin channel can alleviate the floating body effect effectively. However, thin source/drain S/D regions with large series resistance also degrade device performance. To reduce this series resistance, many methods have been proposed to fabricate a raised source/drain structure. 3,4 However, for ultrathin-channel poly-Si TFTs, reducing S/D resis- tance by self-aligned silicide SALICIDE or selective tungsten chemical vapor deposition SWCVD technologies have not been studied before. SWCVD is a good candidate to reduce S/D resis- tance because of its small Si consumption. 5 In this paper, short- channel poly-Si TFTs with ultrathin channel and tungsten-clad S/D W-TFTs are proposed. With a simple process step and conven- tional top-gate structure, W-TFTs can suppress the floating body effect and obtain improved driving current simultaneously. Experimental First, a 30 nm amorphous silicon layer was deposited by low- pressure chemical vapor deposition LPCVD at 550°C on oxidized silicon wafers. After active region patterning, a 60 nm tetraethy- lorthosilicate TEOS oxide layer and subsequently a 300 nm amor- phous silicon layer a-Si were deposited by LPCVD. The a-Si layer was then recrystallized by solid-phase crystallization SPC at 600°C for 24 h. After defining gate by reactive ion etching RIE and removing the oxide on S/D regions by HF dip, n - lightly doped drain LDD implant was performed using phosphorus ions at a dose of 3  10 13 cm -2 . Then, a 200 nm oxide sidewall spacer was formed abutting the gate by conformal deposition of a TEOS oxide layer and subsequent RIE. Next, phosphorus ions at a dose of 5  10 15 cm -2 were implanted to form the n + S/D region, dopants were activated by rapid thermal anneal RTA at 750°C for 20 s. After removing the remaining oxide on S/D regions by diluted HF, wafers were loaded into a W-CVD system ULVAC ERA-1000 to selectively deposit W film on the exposed gate, source, and drain regions. The selective deposition was first dominated by a silicon reduction reaction, which has a self-limiting nature to consume sili- con less than 20 nm. After the formation of an initial thin W film, a SiH 4 reduction reaction took place with a deposition rate of approxi- mately 240 nm/min. The WF 6 /SiH 4 gas flow rate was kept at 40/12 and the process temperature was 300°C. Conventional devices with- out W film deposition were also fabricated to serve as controls. A 500 nm Al film was deposited, patterned, and sintered at 400°C for 30 min to form metal pads. To reduce trap density and improve interface quality, wafers were also immured in an NH 3 plasma gen- erated by plasma-enhanced CVD PECVD at 300°C for 1 h. 6 For W-TFTs, wafers were split to receive the NH 3 plasma treatment either before or after W deposition to study the effects of W-clad S/D structure on blocking the NH 3 molecules from entering the active channel region. A cross-sectional scanning electron micros- copy SEM image of the proposed W-TFT is shown in Fig. 1. A schematic structure is also drawn in the inset of Fig. 1. The W film is about 120 nm thick and the silicon consumption in S/D regions is limited to less than 20 nm. As a result, the contact resistance can be kept low, because the 30 nm channel film is not fully consumed. Results and Discussion Figure 2a depicts the output characteristics ( I D - V D ) of W-TFTs and their conventional counterparts without selective W deposition. The nominal channel width and length are 10 and 3 m, respec- tively. W-TFTs exhibit a larger driving current than conventional * Electrochemical Society Active Member. z E-mail: tcchang@mail.phys.nsysu.edu.tw Figure 1. Cross-sectional SEM image of W-TFT. A schematic cross section of W-TFT is also depicted in the inset. Electrochemical and Solid-State Letters, 7 2 G31-G33 2004 0013-4651/2003/72/G31/3/$7.00 © The Electrochemical Society, Inc. G31