Invited Paper 0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.028 Microelectronics Reliability 45 (2005) 1406–1414 www.elsevier.com/locate/microrel Trends and challenges to ESD and Latch-up designs for nanometer CMOS Technologies G. Boselli  , C. Duvvury Silicon Technology Development, Texas Instruments Inc., Dallas, TX, 75243 Abstract With the rapid scaling of CMOS technologies into the nanometer arena, ESD and Latch-up are becoming reliability threats more complex than ever. This paper will systematically address all the challenges related to robust ESD and Latch-up designs as technology scales. The paper will be divided into three distinct parts. In the first part , the intrinsic technology ESD and Latchup scaling characteristics will be reviewed. Particular emphasis will be devoted to nMOS and pMOS scaling, thin-oxide reliability, ESD diodes, metal lines and Latch-up process sensitivity. In the second part , new circuit requirements and their impact on ESD and Latch-up designs will be presented. The challenges associated to the recently introduced power management techniques, ultra low capacitance applications and SoC design will be discussed. Finally, in the third part , unexpected ESD and Latch-up issues such as premature pMOS triggering, unwarranted stress from the HBM tester relay leading to false HBM evaluation, adjacent signal pins interaction and Latch-up will be presented. In the first part , the intrinsic technology ESD and Latchup scaling characteristics will be reviewed. Particular emphasis will be devoted to nMOS/pMOS scaling (new channel length-related effects, and ballasting techniques), thin-oxide reliability, ESD diodes, metal lines and Latch-up process sensitivity. 1. Introduction Considerable research during the 80’s and 90’s led to a deep understanding of high current device physics, which drove the development of ESD protection concepts for numerous applications still in use nowadays [1,2] In the second part , new circuit requirements and their impact on ESD and Latch-up designs will be presented. In particular, the challenges associated to the recently introduced power management techniques, ultra-low capacitance applications and SoC design will be discussed. However, as the CMOS technologies scale into the nanometer arena, new high current phenomena and stringent circuit requirements are making the ESD design more challenging then ever. This paper is divided into three distinct parts to systematically review all the current and upcoming ESD design challenges. Finally, in the third part , unexpected ESD and Latch-up issues will be reviewed.  Corresponding author. Tel: 001 (972) 927 7055 Fax: 001 (972) 995 1724 e-mail address: g-boselli@ti.com Ó 2005 Elsevier Ltd. All rights reserved.