Abstract—This paper introduces an Ultra Thin Body Silicon Over Insulator Tunneling Field Effect Transistor structure, which shows excellent device characteristics using a CMOS compatible fabrication process. This fabricated TFET structure shows ≤40 mV Sub-threshold Swing (SS), on-state/ off-state current ratio ≥108 and a scaled down Supply Voltage 0.6 Volt at 32nm gate length. The work also includes a detail design parameters study on the on-state/ off-state current ratio and sub-threshold swing. The result is particularly promising for low-power application of the device. Index Terms—SOITFET, UTBTFET, band-to-band tunnelling, sub-threshold swing, TCAD. I. INTRODUCTION Steep Sub-threshold slope devices are of great interest now a day from energy efficiency point of view. As MOSFET are scaled down, the power supply voltage should also be scaled down in order to reduce the power dissipation of the circuit. In order to achieve this goal while maintaining a suitable on-state and off-state current, the sub-threshold swing of the device must be very low [1]. The sub-threshold swing of the MOSFET is theoretically limited by its 60 mV/decade value. In order to overcome this limiting problem some novel devices have been proposed to achieve a sub-60-mV/dec SS such as impact-ionization MOS devices, nano-electromechanical FET, suspended-gate MOSFETs and tunneling FET [2]. The Tunneling FET (TFET) has been considered as a potential candidate among these novel devices due its carrier transport mechanism of band-to-band tunneling. TFET is considered particularly suitable for low-power application due to its extremely low off-state current and very steep sub-threshold slope [3], [4]. This work presents the process flow for the ultra thin body silicon over insulator TFET structure. Simulation results shows that the ultra thin body silicon over insulator TFET structure exhibits a marked improvement in Ion and sub-threshold swing. II. DEVICE STRUCTURE Fig. 1 illustrates the UTB SOI TFET structure which is introduced in this paper. The structure has pick source, channel and drain doping 1×10 20 (Boron), 1×10 14 (Boron), Manuscript received April 12, 2012; revised May 23, 2012. Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman and Kunal Sinha are with the Bengal Engineering and Science University, Shibpur. Partha Sarathi Dasgupta is with the Indian Institute of Management, Calcutta. 5×10 18 (Phosphorus) respectively. The HfO2 and Aluminum are used as gate insulator and gate metal respectively. Both the gate metal and gate insulator thickness are chosen to be 1nm. A 2nm thick SiO 2 layer has been introduced exactly below the gate region and the channel thickness is chosen as 4nm. The gate has an overlap of 3nm with source and drain regions. A Silicon-Germanium layer is used in the source with Germanium mole fraction and concentration as 0.75 and 1×10 20 respectively. Fig. 1. UTB-SOI TFET structure. III. PROCESS FLOW All the simulations were carried out in 2D using Sentaurus TCAD. By using the Sentaurus Process, the UTB SOI TFET structure shown in Fig. 1 is achieved. A. Substrate Oxidation and Etching First a Silicon substrate is taken with 4nm thickness and 68nm width. A 2nm thick SiO2 is grown on the surface by thermal oxidation. Then the oxide is etched out from both the side which gives 32nm oxide length as shown in Fig. 3. This oxide will serve as bulk oxide of the device. Next a 6nm thick Silicon is deposited on the structure and additional Silicon is etched out from the surface in order to make it uniform. B. Phosphorus Doping and Annealing The drain region is formed by Phosphorus doping into the substrate thorough ion implantation. The implantation energy and ion dose are selected as 1KeV and 3.2×10 18 [cm - 3 ] respectively. After the implantation a quick activation (rapid thermal annealing) is done for 1 second at 900 0 C. Finally the doping profile obtained. C. Germanium Implantation Boron Doping and Annealing First Germanium is doped into the source region with a pick concentration 1×10 20 [cm -3 ]. The Germanium concentration is confined within the source region as strictly as possible. Then Boron is doped into the source region thorough ion implantation. The implantation energy and ion dose are An Extremely Low Sub-Threshold Swing UTB SOI Tunnel-FET Structure Suitable for Low-Power Applications Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman, Kunal Sinha, and Partha Sarathi Dasgupta International Journal of Applied Physics and Mathematics, Vol. 2, No. 4, July 2012 240