INTEGRATION OF AN IMPROVED HARVESTER-ON-CHIP CORE DICE ON COMMERCIAL SOI-BASED MEMS TECHNOLOGY G. Murillo 1 *, J. Agustí 1 , G. Abadal 1 , F. Torres 1 , J. Giner 1 , E. Marigó 1 , A. Uranga 1 , N. Barniol 1 1 Dept. Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193-Bellaterra, Spain Abstract: This work presents the design of the fully-dedicated core dice of an energy harvester-on-chip (HoC) with electrostatic transduction. The core dice has been fabricated by using a SOI-BASED MEMS technology which allows us to fix the problems found in the first prototype. The main highlights of this design are the use of ARCHITECH® software, which offers us the possibility of carrying out a parametric design by defining hierarchical blocks, and the advantage of using a SOI silicon layer of 60 μm to fabricate the mechanical suspensions, which increases the robustness and performance of the design. Simulations have been performed in order to validate the final design. Finally, several attempts of assembling the core dice together with a support substrate, by using an ad-hoc bonding technique, have been carrying out. Keywords: Harvester-on-Chip, Energy Scavenging, Silicon-over-Insulator, Electrostatic Transduction INTRODUCTION The basic ideas of the concept of HoC are the use of the whole chip as inertial mass of a damped spring- mass system, and the micromachinable area to define the transduction and anchored parts. The first HoC prototype, which was just a proof-of-concept, was introduced in a previous work [1] and it was fabricated in a CMOS technology. In this case, the core dice has been fabricated by using a SOI-BASED MEMS technology which allows us to fix the problems found in the first prototype. For this design, we have used of ARCHITECH® software, which allow to perform parametric design by defining hierarchical blocks. IMPROVED DESIGN This chip has been designed with the idea of fixing the problems found in the first prototype of this concept [1]. Several conclusions were extracted from the last proof-of-concept prototype. First, there is a trade-off between transduction area and stiffness loss in each individual suspension, with its subsequent size increase and worsening of the vibration direction selectivity, when the cells number is increased. Therefore, the idea of multi-cells, which was introduced with the HoC concept, has to be changed, by joining the cells, in order to decrease the suspensions amount and increasing the number of comb driver fingers and consequently the transduction area. Secondly, the ratio between transduction area and chip volume has to be improved by increasing the comb-driver finger thickness. In order to overcome these two challenges, we have changed from a standard CMOS technology to a commercial SOI- MEMS fabrication technology. The technology selected was MEMSOI from Tronics®. This foundry allows us to use a 60 μm silicon layer to build our fingers and suspensions. This change is translated into an improvement of the resonance movement direction selectivity and an increase of more than one order of magnitude in the transduction density. Fig. 1: Parametric model of the whole chip and detailed scavenging spine model. Typically, the design process of a chip with these features is a tedious work, where after the first design several cycles of simulation-redesign have to be carried out, with the consequence of an increase in difficulty and design time. In this case, we have used ARCHITECH® [2] to parametrically define the chip elements and features and obtain useful simulation results. The advantage of use this type of design procedure is that this software can automatically generate the final device layout. Once we have the parametric scavenger model (see Fig. 1), we can change dynamically parameters, such as comb-driver beams number or the suspensions type, without redrawing the design layout. Only the electrical connection tracks and the test pads had to be manually PowerMEMS 2009, Washington DC, USA, December 1-4, 2009 0-9743611-5-1/PMEMS2009/$20©2009TRF 233