A Novel 1V, 24μW,   Modulator Using Amplifier & Comparator Based Switched Capacitor Technique, with 10-kHz Bandwidth and 64dB SNDR Shafqat Ali, Steve Tanner and Pierre Andre Farine Swiss Federal Institute of Technology (EPFL), 1015 Lausanne, Switzerland. shafqat.ali@epfl.ch Abstract— A new technique, Amplifier and Comparator Based Switched Capacitor (ACBSC) for low voltage switched cap circuits, is presented. ACBSC combines the recently introduced CBSC (comparator based switched capacitor circuit) with an amplifier. The current sources in ACBSC experience less output voltage swing compared to the ones in CBSC. We apply ACBSC to the design of a 3rd-order sigma delta modulator in a 0.18 μm CMOS process technology, with a bandwidth of 10 kHz. Simulations show that the SDM achieves a peak SNDR of higher than 64 dB and consumes 24 μW from 1 Volt supply. Keywords: CBSC; Sigma delta modulator; Low voltage design. I. INTRODUCTION The feature size reduction in CMOS process technology is beneficial for digital circuits, but renders analog design increasingly challenging [1], particularly because of the voltage supply reduction. For instance, high gain amplifiers needed in many analog circuits are difficult to design at low voltages. Consequently, several attempts were made to design switched- capacitor (S-C) circuits without the need for amplifiers [2, 3]. One of the new topologies, called CBSC [3], replaces the op- amps with current sources and comparators. In this paper, we explore the potential of using a low gain amplifier (hence more suitable in modern CMOS technologies) with CBSC. This scheme relaxes the output swing requirements of the current sources. Since the threshold detection comparator in CBSC is implemented as a cascade of amplifiers [3], the power penalty for adding an extra low gain amplifier remains reasonable. After describing ACBSC operation in Section II, the design and simulation results of an ACBSC integrator is presented in Section III. The circuit is used for the design of a third-order single-bit sigma-delta modulator, presented with its expected performance in Section IV. Finally, after comparing the performance of the proposed technique with other approaches in Section V, Section VI concludes the paper. II. ACBSC OPERATION CBSC and ACBSC integrators are shown in Fig. 1 and 2, respectively. The input sample phase for both integrators is the same. The charge transfer phase of the CBSC stage is explained in [3]. In this phase, the output node Vo is charged or discharged until the comparator triggers, indicating that the charge of C1 has been transferred to C2. The current sources, in CBSC, are directly connected to the output node Vo. The charge transfer phase of the ACBSC integrator can be divided into two sub phases (Fig. 3). In the first one, the integrator is operated in a classical way, the amplifier pushes Figure 1: CBSC integrator. Figure 2: ACBSC integrator. Figure 3: Timing of an ACBSC integrator. node Vn close to voltage Vp. At the end of this phase the remaining error is due to the finite amplifier DC gain. In the second sub phase, the circuit passes to CBSC mode: the comparator detects the difference and turns on the respective current source, trying to make Vn equal to Vcm. Ideally, the comparator should make Vn exactly equal to Vcm. As evidenced from Fig. 1 and 2, in ACBSC the current sources experience less variation of output voltage as compared to CBSC. As a result, they can be easily cascoded to achieve high output impedance even when low supply voltage (e.g. 1 V) is used. This significantly reduces the ramp rate variation problem of the CBSC [3].