A 0.6V, 1.3mW CMOS LNA Using Linearity Enhancement Technique Ehsan Kargaran 1 , Mohsen Jamshidi 2 , Abbas Z. Kouzani 3 , and Khalil Mafinezhad 1 1 Microelectronic Laboratory, Sadjad University of Technology, Mashhad, Iran 2 Department of Electrical Engineering, Amirkabir University of Technology, Iran 3 School of Engineering, Deakin University, Geelong, Victoria 3216, Australia Email: E.kargaran725@sadjad.ac.ir Abstract—A highly linear, low voltage, low power, Low Noise Amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP 3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching -1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S 21 ) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V. Index Terms—first Low Noise Amplifier (LNA), folded cascade, high linear, low power, low voltage, current reuse I. INTRODUCTION The increasing demands upon portable wireless devices have motivated the development of CMOS Radio Frequency Integrated Circuits (RFIC). These devices require low power dissipation to maximize battery lifetime. Some low power applications, such as wireless medical telemetry, require the portable devices to operate at low supply voltage with a small battery or environment energy, thus the power and supply voltage constriction is a crucial issue for these designs [1]. On the other hand, due to the possible large interference signals at the input of a Low-Noise Amplifier (LNA), the LNA has to provide high linearity to prevent the intermodulation tones created by the interference signal from corrupting the carrier signal. This linearity improvement should not be at the cost of gain or Noise Figure (NF). This requires the use of linearization techniques implemented with minimal current overhead. In order to improve the linearity of LNAs, several linearization techniques have been proposed recently [2]. In [3], [4], the linearity factor was improved without paying attention to the NF parameter. In [5], linearity was dramatically enhanced, but the presented topology requires a high supply voltage and consumes more power. In this paper, a new implementation of the linearization technique which is Manuscript received October 10, 2015; revised March 30, 2016. recommended for low voltage and low power LNAs is proposed while gain and NF are maintained approximately constant. II. CIRCUIT DESCRIPTION The cascode structure is extensively used in the LNA design; however, it is not suitable for low voltage applications due to its stacking configuration. Since, with the NMOS stacking architecture of the common-source and common gate transistors, relatively large bias voltage is required for transistor biasing, and the performance degrades significantly as the supply voltage decreases. For low-voltage applications, a folded topology is one of the popular structures. As shown in Fig. 1(a), a folded cascode topology, instead of a stacking cascode topology, is adopted to reduce the supply voltage. Although source inductive degeneration is one of the popular methods for input impedance matching, it leads to reducing the LNA gain. Therefore, more power should be consumed to compensate the missing gain. In order to increase the power gain, a new input impedance matching called Parallel Inductor (PI) was presented in details by the author in [1]. The source inductor has been removed and the parasitic gate resistance can be converted to 50Ω by a simple LC matching circuit network. Considering Fig. 1(a), the input impedance of the LNA designed with the PI method can be expressed as [1]: 2 1 1 (( )/ ) ( 1/( )) in PI p p p s Z L R j L C        (1) where 2 1/( ( )) p inM gs R R C   and C gs and R inM are gate to source capacitance and parasitic input resistance of MOSFET, respectively. In addition, L p1 is the inductance which is seen by C s when looking towards the LNA. Therefore, when the input of the LNA is matched, one obtains (ωL p1 ) 2 /R p =50, and ωL p1 =1/(ωC s ), which yields: 50 inM s gs R C C  (2) 2 1 (1 ) 50 p inM gs L R C    (3) International Journal of Electronics and Electrical Engineering Vol. 4, No. 6, December 2016 ©2016 Int. J. Electron. Electr. Eng. 488 doi: 10.18178/ijeee.4.6.488-493