Resistivity of graphene nanowires: Requirements of quality and doping for inter- connect applications Hisao Miyazaki 1 , Masayuki Katagiri 1 , Makoto Takahashi 1 , Yuichi Yamazaki 1 , Daisuke Nishide 1 , Takashi Matsumoto 1 , Makoto Wada 1 , Naoshi Sakuma 1 , Kazuyoshi Ueno 2 , Rika Matsumoto 3 , Akihiro Kajita 1 , and Tadashi Sakai 1 1 Low-power Electronics Association & Project (LEAP), West 7, 16-1 Onogawa, Tsukuba, 305-8569, Japan Phone: +81-879-8264, Email: miyazaki@leap.or.jp 2 Shibaura Inst. of Tech., 3-7-5 Toyosu, Koto, Tokyo, 135-8548 Japan 3 Tokyo Polytechnic Univ., 1583 Iiyama, Atsugi, Kanagawa, 243-0297 Japan Abstract We experimentally and theoretically examined the resistivity of graphene nanowires. An increase of the resistivity in narrow wires agreed well with our calcula- tion in which the edge scattering is taken into account. The quality and doping targets were evaluated in terms of the mean free path and the Fermi level based on the results from the calculation. 1. Introduction Since LSI interconnects are now miniaturized, the need for higher resistivity of the metal interconnects is becoming problematic. Graphene or graphite is an attractive alterna- tive material for use in these interconnects, because its conductivity is potentially higher than metal with an edge state transport [1] or doping by intercalation [2]. However, the quality of graphene and the doping level need to be enhanced in realistic production processes. Their require- ments are quantitatively discussed in terms of the mean free path and the Fermi level in this paper. 2. Experimental We fabricated multilayer graphene (MLG) wires using low-temperature-grown CVD graphene and high-quality Kish graphite as the starting materials (Fig. 1). Plas- ma-enhanced CVD at 600 °C was used to grow the CVD graphene (typically 20 nm thick) on a Ni catalyst layer (30 nm thick) [3]. The graphene layers were exfoliated from the Ni catalyst layers using a support layer and transferred onto SiO 2 /Si substrates after growth [4]. The Kish graphite was transferred onto SiO 2 /Si substrates using a mechanical ex- foliation method [5], becoming 10–48-nm-thick MLG flakes. The MLG films were patterned into 16-nm–10-m-wide and 1-2-m-long wires by using elec- tron beam lithography to form a hard mask and by using oxygen reactive ion etching (RIE), as shown in Fig. 1. The electrical resistance of the wires was measured at room temperature in the four-terminal configuration shown in Fig. 1(b). 3. Results and discussion The resistivity of graphene wires is plotted in Fig. 2 as a function of the wire width W for both the CVD and the Kish graphene. The resistivity of the Kish graphene rapid- ly increases when it is less than 100-nm wide. The CVD Fig. 2 Width dependence of resistivity for Kish (circles) and CVD (triangles) graphene. The curves represent the calculation results for  orig = 200 nm (solid) and 15 nm (dashed) using the common parameters E F = 60 meV, P= 0.5, and T= 300 K. Fig. 1 (a) Procedure for fabricating MLG nanowires. A MLG flake is prepared on a Si/SiO 2 substrate using Kish or CVD graphite as the starting material. Electron beam lithography, deposition, and a lift-off process are used to form the metal (Ti/Au) electrodes and hard masks (SiO 2 ). O 2 RIE is used to remove the unnecessary MLG. (b) and (c) are SEM and TEM images of MLG nanowires. Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials, Tsukuba, 2014, - 1050 - P-4-3 pp1050-1051