!"#$% "
&’ (!) #$% "
!" #$% "
*+%%
,-*%%
-*-+
. . / % $ % /
0"12
Abstract— Scaling down the integrated circuits has resulted in the arousal of number of problems
like interaction between interconnect, crosstalk, time delay etc. These problems can be overcome by
new designs and by use of corresponding novel materials, which may be a solution to these
problems. In the present paper we try to put forward very recent development in the use of novel
materials as interlayer dielectrics (ILDs) having low dielectric constant () for CMOS interconnects.
The materials presented here are porous and hybrid organo-inorganic new generation interlayer
dielectric materials possessing low dielectric constant and better processing properties.
Introduction
Integrated circuits have been scaled down to 45nm and even further. Due to miniaturization of
integrated circuits certain problems like reduction of electrical resistance due to interaction between
the interconnect lines, crosstalk, power dissipation, time delay due to wire capacitance occur. These
problems are delaying the further progress in integrated circuit research like low power, cost,
multifunctional and high speed.
To combat these problems, Aluminium is replaced by Copper in interconnects and damascene
method of processing is applied. Low- materials are being used as interlayer dielectrics (ILDs).
Considerable efforts have been made on the optimization using simulation method for:
i. Design, architecture, sizes of interlayers, interconnects
ii. Use of materials with appropriate thermal and electrical properties
iii. Alternate material to SiO
2
, as inter-layer dielectrics having low dielectric constant.
Thus there are two aspects of research :
i. Design
ii. Materials for ILDs
A material used in these interlayer dielectrics has to face the challenges like:
i. High mechanical strength
ii. High thermal stability (upto 350-400
о
C)
iii. Low moisture content
iv. Low coefficient of thermal expansion to avoid stress in material during fabrication
v. Good adhesion of the material with the substrate
vi. Inertness towards metals used in the circuit
vii. Ease towards etching, damascene process and above all
viii. Breakdown field above 2 MV/cm
There has been great advancement in polymer research and hence it is advantageous to engineer
the polymers into the integrated circuits due to their novel properties which are structural,
constitutional. Porous polymers possess mechanical strength, chemical inertness, thermal stability,
weather resistance, etc.
Applied Mechanics and Materials Vols. 110-116 (2012) pp 5380-5383
Online available since 2011/Oct/24 at www.scientific.net
© (2012) Trans Tech Publications, Switzerland
doi:10.4028/www.scientific.net/AMM.110-116.5380
All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP,
www.ttp.net. (ID: 134.148.29.34, University of Newcastle, Callaghan, Australia-03/09/14,11:31:05)