Ambipolar Memory Devices Based on Reduced Graphene Oxide and Nanoparticles By Sung Myung, Jaesung Park, Hyungwoo Lee, Kwang S. Kim,* and Seunghun Hong* There has been huge interest in advanced nanoelectronic devices based on graphene layers due to their remarkable electrical properties, which include extremely high carrier mobility and the linear energy dispersion relationship. [1–16] However, a lack of methods for mass-production remains a major obstacle for the implementation of these devices in practical applications. The mass fabrication of graphene-based electrical devices requires precise control over the location of the graphene channels on a solid substrate. In addition, for high-performance integrated devices, one should be able to combine graphene devices with high-k dielectrics and control the carrier density in the graphene layers. The conventional doping method that involves the implantation of impurity atoms, however, is not suitable for the integrated devices based on pristine graphene since it will cause permanent damage. [17] Herein, we report a new method for large-scale assembly of graphene oxide (GO) for the fabrication of ambipolar memory devices. In this approach, GO is selectively assembled onto positively charged molecular layers and reduced to obtain the desired device properties. Using this technique, we demonstrate the fabrication and effective operation of floating- gate memory devices. To this end, we sequentially perform the deposition of a dielectric film over the top of a reduced GO junction, the assembly of nanoparticles (NPs), and the fabrication of a top gate. As a proof of concept, we successfully demonstrate that this device can be operated as both conventional conductivity- switching memory and new type-switching memory by adjusting the charge density on the NPs. Importantly, since our method uses only microfabrication processes, it can be utilized immediately by the semiconductor industry and should be a major breakthrough in building innovative electronics. Our memory devices comprise reduced GO pieces and gold NPs that are fabricated by combining the assembly process of nanostructures with conventional microfabrication (Fig. 1). [18,19] First, selected regions of a photoresist layer are removed using standard microfabrication techniques. The substrate is then placed in a solution of 3-aminopropyltriethoxysilane (APTES) to fill the exposed regions of an underlying SiO 2 surface. When the substrate is subsequently placed in a GO solution, GO pieces are assembled selectively onto the amine-terminated APTES regions. The source and drain electrodes are fabricated with the conventional lift-off process. In order to render the GO electrically conductive, the insulating GO is reduced overnight to graphene through exposure to hydrazine vapor. [20,21] Then, a 2-nm-thick Al 2 O 3 film is deposited by the atomic layer deposition (ALD) process using trimethylaluminum and water at 150 8C. The high-k dielectric layer is advantageous as an insulating layer covering the SiO 2 layer. In addition, the ALD process did not damage the GO, unlike chemical vapor deposition on SiO 2 . The methyl-terminated octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) and amine-terminated APTES SAM were patterned onto the Al 2 O 3 film by photolithography as reported in our previous study. [18,19] Here, APTES SAM patterns on the Al 2 O 3 surface were prepared directly above the reduced GO channels. When the patterned substrate was placed in a solution of 30 nm diameter Au NPs, negatively charged Au NPs were assembled onto positively charged APTES SAM. After the NP assembly, a 50-nm-thick Al 2 O 3 layer was deposited as a gate insulator on the NP patterns. Finally, we fabricated top-gate electrodes on the Al 2 O 3 layer. It should be noted that the entire fabrication processes including the assembly of GO pieces and NPs were performed using only conventional microfabrication facilities, implying that our process is readily accessible to industrial applications. Figure 2a shows the well-defined GO patterns on the SiO 2 surface. For quantitative analysis, we measured the ‘‘effective thickness’’, which represents the volume of adsorbed GO pieces per unit area. Previously, the value of ‘‘effective thickness’’ has been utilized to analyze the assembly process of carbon nanotubes. [18] In our work, we first carried out atomic force microscopy (AFM) topography measurements of a GO pattern to measure the volume of adsorbed GO pieces above the underlying APTES layer. The effective thickness was then calculated by dividing the volume by the area of the GO pattern. The results indicate that we achieved GO patterns with an effective thickness of 1.1 nm with a standard deviation of 0.13 nm. The lower inset in Figure 2a shows a reduced GO junction between the source and drain electrodes with a 7 mm width and 3 mm length reduced GO channel. It is clear that we can obtain uniform reduced GO layers using this method for the fabrication of our devices. COMMUNICATION www.MaterialsViews.com www.advmat.de [*] Prof. S. Hong, S. Myung, H. Lee Department of Physics and Astronomy, Seoul National University Seoul 151-747 (Korea) Department of Biophysics and Chemical Biology, Seoul National University Seoul 151-747 (Korea) E-mail: shong@phya.snu.ac.kr Prof. K. S. Kim, J. Park Center for Superfunctional Materials, Department of Chemistry Pohang University of Science and Technology Pohang 790-784 (Korea) E-mail: kim@postech.ac.kr DOI: 10.1002/adma.200903267 Adv. Mater. 2010, 22, 2045–2049 ß 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 2045