Implementation of a Channel Equalizer for OFDM Wireless LANs Abstract This paper presents an implementation of a channel equalizer for a wireless OFDM according to the IEEE 802.11a and Hiperlan/2 standard. In order to implement the equalizer, algorithms of low computational complexity have been analyzed. A rapid prototype design flow is presented and applied to the prototyping of these equalizer algorithms in real time on a FPGA platform. A new point of view in the prototyping design flow and the verification process is achieved through the last generation system level design environments for DSPs into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems, since they allow a high level of functional abstraction with different data types and operators. The implemented channel equalizer reaches a high degree of hardware simplicity and efficiency, covering the standard specifications. 1 Introduction The High Performance Local Radio Area Network (HIPERLAN/2) has been specified by the European Telecommunications Standards Institute (ETSI) for short radio-access on the 5 GHz band for mobile terminals [1]. The standard defines physical layer bit-rates ranging from 6 to 54 Mbit/s. The transmission format on the physical layer is a burst that consists of preamble and data fields. HIPERLAN/2 uses Orthogonal Frequency Division Multiplexing (OFDM) modulation, due to its efficient usage of the available frequency bandwidth and its robustness to channel fading. The channel equalizer is used to correct phase distortion and amplitude attenuation, caused in the signal by the radio channel and the transceiver’s nonlinear device behavior. Therefore, it is necessary to estimate the physical channel in order to obtain the inverse channel estimation coefficients of the model. According to the specifications of the HIPERLAN/2 standard, there are several types of preambles or “training data”, which are inserted into the transmitter at the beginning of each data burst, in order to achieve channel synchronization and estimation [1]. There are two main approaches to estimate channel frequency. The first set of methods uses training data transmitted on each subcarrier. The second approach uses training information transmitted on a subset of the subcarriers. In this paper, we have selected the equalizer algorithm based on the first approach, since HIPERLAN/2 is a packet- type communication system. These WLAN models generally assume that the channel is constant during the length of the data packet. This greatly simplifies the channel estimation problem. It also avoids relative delays between symbols before the first channel estimates are calculated. The goal of this paper is to present the design of a channel equalizer for OFDM WLANs according to the HIPERLAN/2 standard, and an implementation methodology that efficiently maps system level descriptions down to programmable logical devices, in our case Xilinx FPGAs. Therefore, we have selected a high level model from different low-complexity algorithms. Then, we need to adapt it to the channel estimation method used and the selected device. This also implies the use of an environment that allows working with the hardware constraints oriented to the design of data flow systems. This paper is structured as follows. Section 2 presents the HIPERLAN/2 channel models. Section 3, describes the channel equalizer technique using training data. Section 4 presents the environment tools and methodology. Section 5 explains the hardware model of the equalizer. Section 6, presents the algorithm validation and FPGA performance results obtained using Matlab/ Simulink and System Generator tools. Section 7 ends with conclusions. 2 Channel Models HIPERLAN/2 has been developed focusing on two major environments, which determine two different kinds of networks: Domestic Premises Network (DPN) that covers a Pere Martí Universitat de Vic C/. de la Laura, 13 VIC (Barcelona) Spain pere.marti@uvic.es Moisès Serra Universitat de Vic C/. de la Laura, 13 VIC (Barcelona) Spain moises.serra@uvic.es Jordi Carrabina Universitat Autònoma de Barcelona QC2060. ETSE. Campus UAB Bellaterra (Barcelona) Spain jordi.carrabina@uab.es