International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value (2013): 6.14 | Impact Factor (2015): 6.391 Volume 5 Issue 7, July 2016 www.ijsr.net Licensed Under Creative Commons Attribution CC BY Design Approach towards the High Speed Circular Convolution by using UT Technique and High Speed Parallel Adder Jamvant Omkar 1 , Gurpreet Singh 2 1 M.Tech Scholar (VLSI), Trinity Institute of Technology and Research 2 Professor (ECE Department), Trinity Institute of Technology and Research Abstract: Now a day’s digital devices are going to be a high compact and high portable with high speed designing technique. Digital signal processing and image signal processing is the vast area for researchers and convolution is the best technique for these techniques. In this paper we are designing a high speed convolution technique with low area and high speed. Convolution of the two sequences is the just like as multiplication. Here multiplier is the core element for designing the convolution, like wise adder is the main element+ or device for structuring the multiplier. There are three types of the convolution, Circular, linear and graphical. In this paper we are proposing circular convolution technique by using the Vedic mathematics fast calculation technique. Vedic mathematics is the Ancient Indian Fast calculation method. Modified parallel adder will be used for adding the high bit information. All the analysis and simulation will be done by Xilinx 14.2i software with Spartan 3 Series. Keywords: Circular Convolution, Linear Convolution, Parallel Adder, Vedic Multiplier (VM), UrdhwaTriyakbhayam Sutra (UT) 1. Object The demands of the digital devices are increasing drastically. To full fill the facilities of the users we need some properties like low area, high mobility, high speed and low propagation delay. Generally convolution is used in digital signal processing. The object of this paper is to design the high speed convolution especially circular convolution. 2. Introduction High convolution is the core element for digital processor or image processor. With the advent of new era of the digital devices speed of the processor must be high. Processor’s speed can be enhanced by the aid of high speed multiplication and addition of the binary bits. With the latest advanced of VLSI technology we always keep in mind to increase the speed and reduce the area as possible as. Convolution and de-convolution techniques play an important role in digital signal processing and image processing. Convolution is a mathematical way of constructing two signals to form a third signal. on the other hand convolution is the process to the calculate the output signal for given input signal by using impulse response signal. Convolution is basically used in digital filter and correlation applications. Convolution can be segregated as linear, circular convolution and graphical convolution. Graphical method is the best way to represent the convolve of two signals but it is the tedious method,sogenerallyweuselinearandcirculartechnique in digital signal processing. Analysis of convolution depends on multiplier and adder devices. So in this paper we are using Vedic multiplier [1] which is based onUrdhvaTriyagbhayanm Sutra and Parallel high speed adder instead of traditional devices. Multiplication can be done by shifting and adding method but it gives high propagation delay. Another method is Wallace tree algorithm but it is not better than Vedic mathematics calculation. ) ( * ) ( ) ( n g n f n y  In above equation f(n) and g(n) are finite length sequence. ] ) ( * ) ( [ ) (       n k n g k f n y Linear Convolution can be calculated by using above equations. But this is lengthy process. This can be solved byseveral methods so cross multiplication is best method one of them. In the same manner circular convolution can be calculated. 3. Cross and Vertically Multiplication Vedic mathematic is the group of 16 sutras which was proposed by Jagadguru Swami BharathikrishnaTrithaji of GovardhanPeeth, PuriJaganath (1884-1960). UdhvaTriyagbhayam sutra is essential technique for fast multiplication which is based on vertically and cross connections. This method is an essential technique for low power VLSI design and Digital signal processing.UrdhavTriyagbhayam is a novel concept through which throughput is obtained parallel and in short way. Generation of partial products and their summation is obtained using this algorithm which is explained in figure [1]. The main feature of this method that differs from other conventional process is that it reduces the need of resources from process to operate at high frequencies requires. The core factor of Vedic multiplier based on UrdhavaTriyagbhayam method [2] is that as the number of bits increases, area and gate delay increases at a faded rate as compared to other multipliers. Figure [1] gives the idea about the binary cross multiplication by using UdhvaTriyagbhayam Vedic multiplication technique. Paper ID: ART2016329 778