An Accurate Learning-Based Performance/Power Model for System-Level Design of a Multicore Multithreaded Network Processor Mohamad Hafezan Department of Electrical and Computer Engineering University of Tehran Tehran, Iran mohamad_hafezan@ut.ac.ir Hossein Azari Department of Artificial Intelligent (AI Platform) Microsoft Corporation Seattle, WA, USA hoazari@microsoft.com Amir Dabaghan Department of Industrial Engineering Bu-Ali Sina University Hamedan, Iran amirdabaghan@gmail.com Leila Beigi Department of Electrical and Computer Engineering University of Tehran Tehran, Iran leila.beigi@ut.ac.ir Abstract—In the network applications domain, different net- work environments and scenarios demand various line rates, and restrain the design of the network processor by several constraints such as power and area. Additionally, new network services and applications with different processing requirements are increas- ingly emerging day by day. In this regard, having a multi-objective and flexible performance model that can be used to minimize the cost and time of designing network processors is an inevitable need. In this paper, we propose an accurate and fast prediction model that exploits just a few numbers of system-level parameters to es- timate the performance and power of a commercial network pro- cessor, Intel IXP2800. The proposed design methodology uses a non-linear learning algorithm - a combination of the polynomial transformation of design parameters and higher-order spline functions - which in the face of newly introduced applications needs only a small training set, i.e. a small number of simulations, to train the model. Our experimental results show the proposed models can achieve a median error rate as low as 8.7 percent for performance and 2.6 percent for power metric. Keywords—performance model, non-linearity, predictor varia- bles, polynomial transformation, spline functions I. INTRODUCTION Network processors (NPs) are programmable software devices specialized for the high-performance execution of packet processing functions via exploiting the parallel nature of network packets. NPs have been widely used in different scenarios such as network edge and core applications, portable devices, network switches and routers, and so forth, over the past decade. On the other hand, users’ demand for new network services and applications has substantially been growing during these years. These various growing applications demand different line rates and pose different constraints on processing power, chip area, and power consumption. In this regard, having a multi-objective and application-adaptable tool to predict the performance metrics of an NP for the given application and design constraints is highly desirable. In this paper, we propose a method of learning an efficient and reliable model from system-level design parameters to accurately predict the performance and power of a typical NP and verify its prediction precision via statistical measures. We use non-linear regression by exploiting a combination of the polynomial transformation of design parameters and higher- order spline functions to formulate and learn the model optimally. The model then can be used as a performance and power consumption predictor for the NP architecture in the face of new applications. To keep the model flexible to the prospec- tive applications, we use several application-specific parameters to learn the application characteristics and reflect their impact on the model. To speed up the design process, we exploit a small number of system-level design parameters and purposefully avoid using parameters at lower abstraction levels. The size of the design space in our study is nearly 1.5 billion design points. By excluding the microarchitecture level and insignificant parameters from the model’s variables set, it shrinks to about 250 million design points. Overall, our proposed model suggests a fast and flexible de- sign tool for multi-objective exploring of the design space of a typical NP, Intel IXP2800 [1], a commercial multicore multi- threaded network processor. We use a combination of application-specific and system-level parameters together with some mathematical formulations to optimize the model for new configurations or applications. As a result, despite the small number of design parameters in our approach, we obtained a reasonable median error of 8.7 percent for processing power and only 2.6 percent for power consumption. The rest of this paper is organized as follows. Section II briefly reviews related work and the reasons for taking steps toward a system-level, learning-based approach. Section III briefly explains the basic concepts in regression analysis. Section IV describes the architecture model of the Intel IXP2800 network processor. Section V discusses the benchmarks, tools, and simulation environment which we have used in building and evaluating the performance and power models. Section VI presents a general design methodology specifically intended for appropriately designing the understudy NP. Section VII presents a detailed description of our regression approach in developing the performance and power models. Section VIII presents an assessment of the proposed model effectiveness and its prediction power using standard statistics, and finally, Section IX is dedicated to the summary and concluding remarks.