Impact of Low-Doped Substrate Areas on The Reliability of Circuits Subject to EFT Events Radu Secareanu, Olin Hartin, Jim Feddeler, Richard Moseley, John Shepherd, Bertrand Vrignon, Jian Yang, Qiang Li, Hongwei Zhao, Waley Li, Linpeng Wei, Emre Salman, Richard Wang, Dan Blomberg, and Patrice Parris Freescale Semiconductor, Inc. Abstract —Externalstresses,suchasthosegenerated due to Electrical Fast Transient (EFT) events, gener- ate over-voltages which may result in reliability fail- ures at the IC level either in the form of recoverable or permanent damage of the IC. In the present pa- per, the relationship between the technology charac- teristicswithinadesignframeworkandthepermanent failures that such an EFT event can produce are dis- cussed. Solutions to minimize the impact of such EFT events are presented. I. Introduction The burst of over-voltage pulses characterizing an EFT event [1] is generally associated with external turn-on/turn-off or switching events such as those of relays of inductive/capacitive loads and electrical mo- tors [2]. Over-voltages are generated on the external cables, propagating to any connected electronic com- ponent. The impact of these pulses on an IC can be observed as electrical failure by means of such mechanisms as breakdown and latch-up [3, 4]. The protection against such over-voltages is required to be implemented predominantly at the IC level, since board-level solutions generally add noticeably to the cost of the final application. I/O level clamp circuits can protect the circuit against such over-voltages [3, 5], while latch-up rules can improve circuit latch-up immunity. Technology options may have consequences such as a greater susceptibility to EFT related over-voltages, which may require design changes to preserve a ro- bust solution in this environment. The relationship between technology and IC reliability when the IC is subject to EFT induced over-voltages is the focus of this paper. Specifically, the focus is on EFT-induced device breakdown. The remainder of the paper is organized as follows. The IC environment for the subject reliability issue is presented in Section II. Results are described in Section III. The paper is concluded in Section IV. II. Synopsis Low-doped substrate areas represent a technology option for technologies supporting high voltage de- vices. Such high-voltage devices are used in various blocks across the IC, including the I/O pads. Since the I/O pads represent the interface with the outside world, devices in pad circuits are most prone to be affected by occurrences like the over-voltages gener- ated by EFT events. Fig. 1. EFT induced device failure Fig. 2. EFT pulse burst. Burst duration 15ms@5KHz or 0.75ms@100KHz, with burst repetition of 300ms. Protection circuits, including clamps, are designed to protect the I/Os. However, during the over- voltage bursts of an EFT event, transients lead to 978-1-4244-8631-1/10/$26.00 ⓒ2010 IEEE ISOCC 2010 - 21 -