Automatic relocking of an FPGA-based PID controller using a bandpass-filtering approach Alexander Hungenberg supervised by Ludwig de Clercq Vlad Negnevitsky and Prof. Dr. Jonathan Home Trapped Ion Quantum Information Group Department of Physics, ETH Zurich August 21, 2013 Abstract This report describes a discrete-time filter approach to improve the stability of PID controlled locks with respect to infrequent and comparatively large disturbances that exceed the usable error signal range. The concept has been implemented with Verilog on an FPGA and was tested on several systems of varying intrinsic stability. Further work has been put into the PyQt based configuration interface to allow completely asynchronous data streaming of input and output channels as well as configuration updates on a single serial communication channel. 1