PRZEGLĄD ELEKTROTECHNICZNY, ISSN 0033-2097, R. 90 NR 5/2014 201 Md. Syedul Amin, Lim Meng Rong, Mamun Bin Ibne Reaz, Fazida Hanim Hashim, Noorfazila Kamal Universiti Kebangsaan Malaysia Design and analyses of a low power linear voltage regulator in 0.18um CMOS process Abstract. Linear voltage regulator is inevitable in most electronic systems and demands low power and low area. A low dropout (LDO) linear voltage regulator is proposed in this paper by utilizing Current Feedback Amplifier (CFA) technology. The design achieves low power and low area by reducing the internal compensation capacitor and resistors. The simulated result shows that the design consumes only 567.1370pW which is 35% less than the reference circuit. The design also achieves low area and higher gain. Streszczenie. W artykule omówiono liniowy regulator napięcia wykorzystujący koncepcję LDO (low dropout ). Układ wykorzystuje wzmacniacz z prądowym sprzężeniem zwrotnym CFA I technologię CMOS. Zrealizowano układ pobierający o 35% mniej energii niż układy znane z literatury. Projekt i analiza regulatora napięcia o małym poborze mocy wykonanego w technologii CMOS 0.18 m Keywords: CMOS, low dropout, voltage regulator. Słowa kluczowe: regulator napięcia, low dropout, technologia CMOS doi:10.12915/pe.2014.05.45 Introduction System on Chip (SoC), modern communication systems including Wireless Local Area Network (WLAN), Radio Frequency Identification (RFID) etc are becoming increasingly popular day by day [1-4]. These systems demands low cost, high integrability and small size [5,6]. Power management is an essential device in these systems. Over-load protection, over-heat shield, stabilization, low power and low area are the essential features of the power management devices to assure the correct operation of these systems [7]. The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology allows power management devices to achieve these criteria [8-10]. LDO linear voltage regulator is widely used in power management devices [11]. LDOs are one of the most critical modules as it is able to provide a nearly constant DC voltage for all the electronic systems. To regulate the performance (line and load regulation) transient overshoot and undershoot are required. On the other hand, to characterise, the power (output current, quiescent current, input and output voltage, and power and current efficiency) is necessary. Therefore, the LDOs need to be carefully designed to enhance the system stability in various operating condition. LDOs contain the error amplifiers to detect the error between the output voltage and the reference. Error amplifier controls the pass transistor when the current passes through the output capacitor. Fast rejection of steep transient load variations, input voltage and loads are the metrics needed to be fulfilled when designing the LDO [12,13]. There are several methods to design the LDO such as pole-zero cancellation method, dual loop feedback and current-mode feedback buffer amplifier, voltage current source and flipped voltage follower to improve the stability and transient response [14-16]. Saberkari et al. proposed a current feedback amplifier for the fast transient response and regulation [17]. Dynamic biasing of derivative feedback was used in an ultra low power capless LDO by Jorge et al. [18]. Wang et al. improved the operating frequency by using the nested feedback loops in LDO linear voltage regulator [19]. However, none of the design could avoid numerous re- sistors and capacitors. A low power LDO linear voltage re- gulator is proposed in this paper by reducing the number of the resistors and capacitors by utilizing the CFA technology. Methodology The proposed LDO linear voltage regulator is the modification of the [17] as shown in Fig. 1. The reference circuit was built up using CFA topology. Open-loop voltage follower with output local current feedback based on a level- shifted slipped voltage follower (LSFVF) includes in CFA. Fig.1. Reference circuit diagram [17] The CFA consists of a pass transistor Mp, a class AB voltage follower M1-M12, an inverting output buffer (M13, M14). There are two feedback networks in that circuit which is R1 and R2. V ref is fed into the circuit to ensure no DC current drain. When load current increases, Vout is decreased. At the same time, the terminal voltage at M3, M4 and gate voltage M7, M8, M5 and M6 is also affected. The current passes through transistors (M7, M9, and M11) but the current is decreased at transistor M8, M10, M12. The voltage is increased at M13 but decreases at Mp. The proposed design reduces the complexity of the above mentioned circuit by reducing resistors and internal compensation capacitor. The schematic diagram of the proposed LDO linear voltage regulator is shown in Fig. 2. The parameters used for the proposed design are Resr=2kΏ, Vbp, Vbn and Vref =3V. Result and Discussion The proposed voltage regulator was designed and simulated in 0.18-μm CMOS process with the Design Architect (DA-IC) and IC station tools of Mentor graphics. The 27 0 C operating condition has been set for the reference LDO and the proposed LDO. The width and length of the transistors are shown in Table 1.