DESIGN OF A DIGITALLY PROGRAMMABLE DELAY-LOCKED- LOOP FOR A LOW-COST ULTRA WIDE BAND RADAR RECEIVER N. Paulino 1,2 ,M. Serrazina 1,2 , J. Goes 1,2 , A. Steiger-Garção 1,2 1 UNINOVA - CRI Campus da Faculdade de Ciências e Tecnologia 2825 – 114 Monte da Caparica – PORTUGAL E-mail: nunop@uninova.pt 2 Faculdade de Ciências e Tecnologia Campus da Faculdade de Ciências e Tecnologia 2825 – 114 Caparica – PORTUGAL E-mail: pc-dee@uninova.pt ABSTRACT This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Tradi- tional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this pa- per uses a ΣΔ modulator to generate a delay unaffected by match- ing and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps. 1. INTRODUCTION Recently, the FCC approved new regulations regarding the use of ultra wide band signals (UBW) [1]. Using these sig- nals it is possible to build low-cost short-range RADAR ranging systems such as the one described in [2]. These sys- tems work by measuring the travel time of a signal from the transmitter to the target and back to the receiver. In order to measure this time it is necessary to compare the received signal with a delayed version of the transmitted signal until an echo is found. The target range can be determined from this delay. Traditionally-digitally programmable delay lines are real- ized using a cascade of delay elements and selecting the output of the element corresponding to the desired delay. Typically this delay line is inserted into a delay-locked-loop (DLL) to guaranty that the delay is not affected by process and temperature variations. This architecture is unavoidable if several delayed versions of the master clock are needed. This type delay line suffers from element mismatch, result- ing in limited delay resolution [3,4]. Another problem is that if a small delay step is required the delay line will be com- posed of large number of delay elements, each one with the small delay step. Normally, a delay element needs a large current to realize a small delay and as a consequence, the overall power dissipation will be large. The architecture presented in this paper is capable of gener- ating a digitally programmable delay whose resolution is not affected by element mismatch and is only limited by the response time to a new programming code. The current in the delay elements is limited by the required jitter noise in the output clock due to the circuit’s noise (thermal and flicker). 2. ARCHITECTURE OF THE PROGRAMABLE DLL A DLL, such as the one depicted in Fig. 1, is a feedback loop, where the delay produced by a voltage controlled de- lay line (VCDL) in a clock signal, is adjusted to be equal to one or more periods of the reference clock. This loop works in a similar way to a Phase Locked Loop (PLL) with the difference that the input frequency is always equal to the output frequency. The loop compares the phase (delay) of the reference clock with the phase of the delayed clock us- ing a phase detector (PD) that, in turn, drives a charge pump (CP). The output of the CP goes trough a low-pass filter and the resulting voltage is used to control the delay in the VCDL. The loop will stop adjusting the control voltage when the rising edges of both clocks coincide. Normally the input clock of the VCDL is the same clock signal used as the reference clock. Phase comp Lowpass Filter Charge Pump u d Reference clock clock Delayed clock Control voltage Fig. 1: Block diagram of a Delay Lock Loop. If two different clock signals, with the same frequency, are used as the reference clock and the input clock for the VCDL, the loop will try to adjust the VCDL to produce a delay equal to the average delay between the two clock sig- nals, that causes the rising edges of both clock signals to coincide. The reference clock does not need to be a clean signal (i.e. with low jitter noise) because the DLL will act as a low pass filter that will eliminate the excess jitter noise from the reference clock. The jitter noise from the input clock of VCDL and the jitter noise introduced by the VCDL will not be affected by the loop; the first is typically very low if a crystal oscillator is used. The rms jitter noise intro- duced by the VCDL can be around 2 to 7 ps by careful de- sign it [5-7]. In this paper, this noise will not be included in the analysis because we are only interested in the jitter noise introduced by the architecture. The noisy reference clock is generated switching from the clean input master clock and a delayed version of this clock (with a fixed delay equal to