Abstract—In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the existing clock gating methods like data- driven clock gating and Auto-Gated flip-flops (AGFF) by allotting a full clock cycle for the determination of the clock enabling signals. Further to reduce the power consumption in LACG technique, FFs can be grouped so that they share a common clock enabling signal. Simulation results show that the novel grouped LFSR with LACG achieves 15.03% power savings than conventional LFSR with LACG and 44.87% than data-driven clock gating. Keywords—AGFF, data-driven, LACG, LFSR. I. INTRODUCTION HE sequential circuits in a system are considered major contributors to the dynamic power consumption since one input of sequential circuits is the clock, which is the only signal that switches all the time. In addition, the clock signal tends to be highly loaded [1]. One of the major dynamic power consumers in computing and consumer electronics products is the system’s clock signal, which is responsible for 30% - 70% of the total dynamic power consumption [2]. Ordinarily, when a logic unit is clocked, its underlying sequential elements receive the clock signal, regardless of whether or not they will toggle in the next cycle. With clock gating, the clock signals ANDed with explicitly predefined enable signals [3], [4]. Clock gating is employed at all levels like system architecture, block design, logic design, and gates [5]. LFSR is a sequential circuit commonly used in Built In Self Test (BIST), Signature analysis and in Spread spectrum communications. In the applications like pseudo-random bit generators (PRBGs), linear feedback shift register is used to produce a random sequence. A good PRBG must be characterized by repeatability (i.e. giving the same output sequence when the same seed is used) and randomness (i.e., passing the most common standard tests and giving good statistical properties) [6]. Today, hardware implementation of the PRBGs is almost always made up of the well-known Dr.R.Manjith is with the Dr.Sivanthi Aditanar College of Engineering, Tiruchendur, 628215; Taminlnadu; India (phone: +91-9994999724; e-mail: manjithkmr@gmail.com). C. Muthukumari was with the Dr. Sivanthi Aditanar College of Engineering, Tiruchendur, 6281215, Tamilnadu, India. linear-feedback shift register whose generic circuit is reported in Fig. 1. This circuit is very simple to be implemented, but since the clock-path of all flip-flops (FFs) toggle at every clock cycle, they consume a significant amount of power. This problem was extensively addressed in [7]. The scheme based on gated clock design for LFSR is proposed in [6]. This design achieves better power result but due to hardware overhead involved this may not work for large applications. Different clock gating techniques have been used to minimize the clock power consumption, as it is the main source of chip power consumption. Deactivating the clock signal leads to reduced power consumptions of both its internal nodes and clock lines, but the overhead involved limits its use in low data switching situations. The main purpose of this project is to reduce the clock gated flip-flop overhead and make it applicable to data signals with higher switching activity. In conventional synchronous designs, all one-bit FFs are considered as independent components. In the recent years, as the technology advances the minimum size of the clock drivers can trigger more than one FF. As a result, grouping 1- bit FFs can reduce the total clock dynamic power consumption. FFs are grouped to reduce the hardware overhead so that clock enabling signal is shared between them. It is done by adding the enabling signals of the individual FFs [3] using OR gate. Finding the optimal grouping is the key for maximizing the power savings. To make LACG a more successful one, flip-flops are grouped which makes better power reduction. II. LINEAR FEEDBACK SHIFT REGISTER LFSR is a well-known circuit for pseudo-random number generation, which consists of N registers connected together as a shift register. The input to the LFSR comes from the XOR of particular bits of the register. On reset, the registers must be initialized to a non-zero value (e.g. all 1’s). At each clock tick, the feedback function is evaluated using the input from tapped bits. The result is shifted into the leftmost bit of the register and the rightmost bit is shifted into the output [8]. The LFSR is an example of maximal length shift register because its output sequences through all 2 N -1 combinations (excluding all 0’s) which is shown in Fig. 1. The inputs fed to the XOR are called the tap sequence and are often specified with a characteristic polynomial. For example, 4 – bit LFSR has characteristic polynomial 1+x 3 +x 4 because the taps come after the 3 rd and 4 th registers. LFSR sequences have been widely used in many important applications, such as wireless communications, bit error rate measurements, radar, error- Dynamic Power Reduction in Sequential Circuits Using Look Ahead Clock Gating Technique R. Manjith, C. Muthukumari T World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:9, No:2, 2015 252 International Scholarly and Scientific Research & Innovation 9(2) 2015 ISNI:0000000091950263 Open Science Index, Electronics and Communication Engineering Vol:9, No:2, 2015 publications.waset.org/10002850/pdf