Journal of ELECTRICAL ENGINEERING, VOL. 59, NO. 2, 2008, 81–85 COMPARISON OF A STANDARD AND A SCHOTTKY DUAL GATE MOSFET Juraj Racko * — Ralf Granzner ** — Frank Schwierz ** — Juraj Breza * — Daniel Donoval * — Ondrej Kuˇ cera * — Peter Pinteˇ s * The article presents modelling and simulation of the electrical properties of Schottky dual gate (DG) MOSFET structures. The contribution focuses on the inﬂuence of the design parameters upon the properties of the DG MOSFET. The design parameters strongly aﬀect the slope of the transfer characteristics and the magnitude of leakage currents because in nanometer structures they have a substantial inﬂuence on band-to-band tunnelling in the vicinity of the drain. The active region of the transistor structure must be viewed upon as a quantum well whose parameters aﬀect the eﬀective bandgap width, which in turn has a key inﬂuence in the model of band-to-band tunnelling. Keywords: Schottky dual gate, MOSFET 1 INTRODUCTION AND THEORY The most serious issue in shrinking the dimension of MOS transistors is the Short Channel Eﬀect (SCE). It brings about complications in the production of CMOS structures. Small changes in the length of the channel re- sult in considerable variations in the threshold voltage. In the current CMOS technology, this phenomenon is sup- pressed by high doping of the regions around the source and drain junctions. The high carrier concentration in these regions causes a decrease in the mobility of free charge carriers. It is this very eﬀect of SCE that motivates further investigations of novel MOS structures that might lead to possible integration of transistors with channel lengths in the nanometer range [1]. One of the promising devices of the new CMOS technology is the dual gate thin ﬁlm transistor, in the literature referred to as DG-MOS (Dual-Gate MOS). It has a lot of variations. We have designed, in ISE MDRAW, a 2-dimensional standard DG MOSFET structure (Fig. 1a) and a Schot- tky DG MOSFET (Fig. 1b) with a 1 nm thick SiO 2 gate and metal gate length L MG = 30 nm. The concentration proﬁle of the semiconductor with a heavily doped region n + -Si (5 × 10 19 cm -3 ) is shown in Fig. 2. The transitions between the n + region and the undoped region were sim- ulated by an exponential proﬁle with a decrease of donor concentration from the maximum value by three orders of magnitude at a length of 8.4 nm. The ISE DESSIS calculator was used to simulate the electric properties of the designed standard and Schot- tky DG MOSFETs. Within the calculator, the fundamen- tal equations were based on the drift-diﬀusion model of charge transport with Fermi-Dirac statistics, the Lom- bardi and Masetti models for low ﬁeld mobility, and the Caughey-Thomas/Canali model for velocity saturation with default DESSIS parameters for silicon. Since the Fig. 1. Two-dimensional standard DG MOSFET structure (a), and Schottky DG MOSFET structure (b) with a 1 nm thick SiO 2 gate and metal gate length L MG = 30 nm. ∗ Slovak University of Technology, Ilkoviˇ cova 3, 812 19 Bratislava, Slovakia; juraj.racko@stuba.sk; ∗∗ Technical University of Ilmenau, PF 100565, 98684 Ilmenau, Germany ISSN 1335-3632 c  2008 FEI STU