Introduction Scan compression is a critical technology for addressing the rapid rise of test cost without sacrifcing coverage requirements. It has become widely adopted throughout the semiconductor industry but is facing challenges. The rise of safety-critical semiconductors demands not just high coverage, but also the ability to verify that the design is working in the feld. Traditional approaches have used discrete scan compression and LBIST, as shown by Figure 1. Issues with additional area overhead and routing congestion limit the effectiveness of this architecture. Figure 1: Traditional discrete LBIST and scan compression Unifed Compression and LBIST in a Physically Aware Environment By Christos Papameletis, Principal Software Engineer; Vivek Chickermane, Sr. Group Director R&D, Cadence Unifed compression is a new approach that unifes scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confdent path to high-quality test. On a sample design, area savings of 35-47%, and scan wirelength savings of 63-77% for the same channel length can be demonstrated. Also, with the same area and scan wirelength budget, the channel length could instead be reduced by half to reduce the overall test time with the same fault coverage. Discrete Compression Macro scan channels LBIST Macro (Control, Clocking … ) PRPG MASK MASK MISR Spreader XOR Decompressor XOR Decompressor Sequential Decompressor Contents Introduction ......................................1 Unifed Compression: Architecture ....2 Unifed Compression: Results ............3 Conclusion ........................................4 References .........................................4