Temperature dependent transfer characteristics of graphene field effect transistors fabricated using photolithography Gunasekaran Venugopal a, b , S.-J. Kim c, * a Nano Materials and System Laboratory, Department of Mechanical System Engineering, School of Engineering, Jeju National University, Jeju 690-756, Republic of Korea b Faculty of Nanotechnology Department, School of Nanoscience and Nanotechnology, Karunya University, Coimbatore- 641114, Tamil Nadu, India c Faculty of Mechatronics Engineering and Research Institute of Advanced Technology, Jeju National University, Jeju 690-756, Republic of Korea article info Article history: Received 29 June 2010 Accepted 7 March 2011 Available online 16 March 2011 Keywords: Photolithographic Graphene field effect transistors Transconductance Mobility abstract We report on the temperature dependent transport characteristics of graphene field effect transistors (G-FETs) fabricated using photolithographic technique. Monolayer graphene layers were selected for the fabrication of electronic devices and the fabricated devices were further annealed in Ar/H 2 at 200  C. The temperature dependence of resistance of the graphene flake shows semiconductor-type behavior. The resistance increases about one order of magnitude upon cooling from 300 K to 8 K. Our observations are good in agreement with the previously reported temperature behavior of monolayer graphene nanoribbons and reduced graphene oxide. A higher drain-current modulation in negative back-gate field with current minimum (the Dirac point) is observed at V GS w 2.75 V. The carrier mobilities were determined from the measured transconductance and obtained mobilities are less than the conductivity and mobility of pristine graphene. The reason could be discussed in detail with variable range hopping mechanism which is consistent to our resistance/temperature data. Ó 2011 Elsevier B.V. All rights reserved. 1. Introduction Graphene, a single sheet of graphite, receives considerable attention from both physics and technological points of view because of their unique properties arising from its peculiar elec- tronic 2-D band structure, and an extraordinary high carrier mobility of 200,000 cm 2 V 1 s 1 [1]. The unique topology of hexagonal arrangement of carbon atoms provides an unusual energy dispersion relation near the Fermi energy in graphene. The energy dispersion near the charge neutrality points, termed as the Dirac points [2]. Near the Dirac point, the 2-dimensional (2D) energy spectrum is linear, and thus the electrons always move at the constant speed, the Fermi velocity y F z 10 6 m/s [3]. In addition, graphene has excellent mechanical and thermal properties [4,5]. It is a semimetal with an extremely small overlap between the valence and the conduction band (zero-gap material). In its 3-D graphite structure, graphene sheets are weakly coupled between the layers with van der Waals forces [6]. The carrier transport in graphene takes place in the p-orbitals perpendicular to the surface [7]. The major advantage of graphene over CNTs is its planar form, which generally allows for highly developed top-down CMOS- compatible process flows. These properties make graphene a promising material for future nano-electronic applications. There are many approaches reported so far for graphene synthesis by chemical vapor deposition (CVD) on a substrate [8], sublimating Si from the surface of SiC single crystal [9] and various wet-chemistry based methods [10]. Even the transfer processes used in CVD technique, may not be appropriate for applications using a large substrate, including large-scale integrated circuits (LSIs) and large screen displays [11]. We strongly believe that gra- phene channels should be formed directly on a substrate without such transfer processes. However, up to now no low-cost proce- dures have delivered high quality graphene for practical electronic device applications. Graphene can be used as the conducting channel for field effect transistor (G-FET) applications with a variety of gate configuration. Novoselov et al. [3] demonstrated the first graphene-FET device with back-gate configuration on n-doped Si substrate and 300 nm thick thermal oxide SiO 2 . The main advantage of using back-gate configuration is the utilization of top surface of graphene for conduction modulation [12]. Lithography-free fabrication techniques have been reported in Ref. [13], however the procedures are complicated and yield devices that are restricted to simple geometries [14]. In this presentation, we first describe the sample fabrication processes of single layer graphene devices * Corresponding author. Tel.: þ82 64 754 3715; fax: þ82 64 756 3886. E-mail address: kimsangj@jejunu.ac.kr (S.-J. Kim). Contents lists available at ScienceDirect Current Applied Physics journal homepage: www.elsevier.com/locate/cap 1567-1739/$ e see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.cap.2011.03.030 Current Applied Physics 11 (2011) S381eS384