Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression Balaji Vaidyanathan, Yuan Xie Department of Computer Science and Engineering Pennsylvania State University, PA - 16801 bvaidyan, yuanxie @cse.psu.edu ABSTRACT Code compression techniques have been proposed to mitigate the problem of limited memory resources in embedded systems. As technology scales, reducing on-chip bus energy consumption is becoming important for embedded system designers. In this paper, we propose a crosstalk-aware energy-efficient code compression scheme, which can reduce inter-wire coupling transition induced instruction bus energy consumption, without sacrificing compression ratio. The experimental results show that the bus power consumption due to inter-wire coupling transition alone is reduced by 42-68% and the total bus power consumption is reduced by 55-71% for TMS320C6x benchmarks. I. I NTRODUCTION Code size reduction is one of the most important design goals for embedded systems, because embedded systems are space and cost sensitive and memory is one of the most restricted resources. As technology scales, on-chip bus power consumption becomes an important part of the overall embedded system power consumption. Lahiri et al. [7] demonstrated that the on-chip bus can consume significant power that is comparable to other well-known primary sources of power consumption (such as embedded processor and caches). Another impact of technology scaling is the increas- ing importance of bus crosstalk. The inter-wire capacitance becomes dominant compared to the wire-to-substrate capac- itance (self capacitance) [3], and the power consumption due to crosstalk induced coupling capacitance can dominate the power consumption due to the self capacitance. Even though the primary goal of code compression tech- niques is to reduce the size of the instruction memory such that the system cost is reduced, it is essentially a re-encoding of the instruction bus and can be used as a scheme to reduce the instruction bus power consumption and crosstalk. In this paper, we demonstrate a scheme that can efficiently reduce bus power consumption and crosstalk without sacrificing the compression ratio, by using a Variable-to-Fixed (V2F) code compression technique. The rest of the paper is organized as follows: Section II reviews related work; Section III gives a brief introduction to code compression algorithm we are using; Section IV de- scribe the scheme to reduce the inter-wire coupling transition and hence the total bus power consumption via the codeword assignment for code compression algorithm; Section V shows the experimental result and Section VI concludes the paper. II. RELATED WORK There have been various approaches to code compression, including compiler techniques [8], ISA modification (which modifies or customizes the original instruction set architec- ture), as well as using existing data compression algorithms [1][9]. Many techniques have been proposed to reduce bus energy by exploiting the data and address access patterns. For example, The Bus-Invert Code [10] toggles the polarity of the signals according to the Hamming distance (the number of differing bits) between two consecutive data values; The T0 code [11] uses an extra line to indicate whether the bus is in normal mode or increasing address. However, many techniques to reduce address bus toggling can not be applied to the instruction bus, since the bits transferred on the instruction bus are highly irregular. Therefore, very few research efforts have been applied to reduce the instruction bus energy consumption. Recently Petrov et al. [5] proposed a low power encoding framework for embedded processor instruction buses, using efficient instruction transformation so as to minimize the bit transitions on the instruction bus lines. Various spatial and temporal redundant bus encoding schemes to reduce bus crosstalk incur extra performance or area penalties. For example, Victor et al. [4] have proposed self-shielding codes which eliminate the worst case crosstalk. Khan et al. [3] described a coupled crosstalk and power opti- mization methodology for eliminating worst crosstalk and re- ducing power using spatially redundant LWC code. However, the bus architecture is changed to accommodate redundant signals which certainly affect bus performance, area, and power. The contribution of this paper is to propose an encoding methodology to code compression scheme, such that the crosstalk induced power consumption on the instruction bus is reduced. We demonstrate that, by clever encoding, instruction bus power reduction can be achieved as a by-product of code compression, incurring no extra delay, power, or area over- head compared to the original code compression mechanism. To the best of our knowledge, this is the first crosstalk aware energy efficient encoding scheme for instruction bus through code compression. III. CODE COMPRESSION ALGORITHM The code compression algorithm we used belongs to Variable-to-Fixed (V2F) coding [1]. It is different from Huff- man coding or other fixed-to-variable coding in that it maps variable-length bit sequences into fixed-length bit sequences. In other words, all codewords are of equal length. This characteristic will be exploited in Section 4 to help reducing bus crosstalk and power consumption. 193 0-7803-9782-7/06/$20.00 ©2006 IEEE