Leakage Optimized DECAP Design for FPGAs Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan Department of Computer Science and Engineering Pennsylvania State University PA, USA {bvaidyan, yuanxie, vijay}@cse.psu.edu Luo Rong EE Department Tsinghua University Beijing, P.R. China luorong@tsinghua.edu.cn Abstract— On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associated with it and is estimated to increase with technology scaling. A recent work has proposed a gated decap structure to reduce leakage in decaps. Their work analyzes leakage saving obtained by implementing gated decap structure in a pipelined super scalar core. FPGAs on the otherhand face similar leakage problem associated with decaps in their un- mapped regions. We analyze here the leakage saving due to gated decap structure in FPGAs. With the on-chip gated decap structure we do uniform placement of decaps that achieves decap leakage savings of 7-60% with 39% on an average for various MCNC benchmarks mapped on to the FPGA device. I. I NTRODUCTION Similar to ASICs, FPGAs are moving to-wards increased integration with rapid technology scaling. Due to this tech- nology scaling current consumption is predicted to follow an exponential trend. This increasing current is attributed to higher density of device integration and higher static power consumption aggravated by process variation [1] as technology scales below 100nm. Consequently power grid design is a growing concern due to this increased current consumption and parasitics associated with the power grid as they aggravate the IR drop and Ldi/dt noise. Power supply integrity is becoming an issue in FP- GAs [8] as a byproduct of reducing supply voltage with the shrinking process geometries. Currently Packaging solutions like placement of off-chip decoupling capacitors is one of the post-manufacture solutions which can mitigate supply noise for FPGAs. But with off-chip decap the impedance response of the power grid is found to be linearly related to frequency [2]. Xilinx ASMBL architecture [8] supports internal power and ground pads which provides uniform power distribution across the FPGA device. Another solution popular in ASIC domain is the addition of on-chip decap to keep the power noise within limits at higher frequency of operation. These on-chip decaps have to be manufactured into the chip, so its placement has to be decided at design time. There has been work in the ASIC domain which analyzes the current consumption profile at design time and selectively places decaps on-chip [3]. FPGAs in contrast have diverse designs mapped onto them which can lead to loads varying temporarily and spatially across designs. Hence the on- chip decap needs to be placed uniformly over the chip to 0 This work was supported in parts by grants from NSF 0454123 and GSRC overcome supply noise. This ad-hoc placement of decaps in FPGA can have area and leakage power overheads. Area overhead is due to excessive placement of decaps that takes care of supply noise for any arbitrarily mapped design. Leakage power overhead is due to the presence of unused on- chip decaps in part of the chip where no design is mapped. We propose here a run-time on-chip decap activation to cater dynamically varying transient loads and also reduce leakage power overheads associated with having unused decaps on- chip. This paper is organized as follows. Section II reviews related work and touches upon the direction of our work. Models for power grid, decap and current consumption in FPGA are explained in section III. Section IV explains the methodology and experimental setup used. Results are provided in section V. Section VI concludes with possible future work. II. RELATED WORK There are two popular static design solutions to mitigate supply drop. They are supply wire thickening in places where IR drop is expected to be high [13] and insertion of on- chip decaps providing local supply of charge [10] to lessen dynamic voltage fluctuation. As Current density increases with technology scaling an intelligent placement of decaps is necessary in places where activity is high. Decaps placed far away from noisy nodes lead to insufficient noise reduction. An optimal placement of minimum-sized decap is proposed for power noise reduction in standard-cell based ASIC design [14]. On-chip decaps are typically designed using MOS based thin gate oxide transistors which have excessive gate leakage currents for gate oxide thickness below 20 ˚ A. Fu et al. [11] proposed a power grid optimization algo- rithm for power supply noise reduction taking decap leakage and routing area as additional optimization criteria. Their work assumes that the on-chip decap placement is known at design time so that the wire sizing can be done in places where the decap leakage is high. FPGAs have current consumption profile which is unknown at design time. The mapped designs decides the current consumption profile of the chip at configuration time. Hence a large number of on-chip decaps are necessary to achieve robust power grid design in FPGA catering to different designs mapped onto it. Consequently there will be more unused on-chip decaps in that part of the FPGA where a design is not mapped. These unused decaps have leakage overheads associated with them and the leakage power for these decaps is expected 960 1-4244-0387-1/06/$20.00 c 2006 IEEE